16SP100M datasheet(16/23 Pages) NSC

16 / 23 page

Application Information (Continued)

One popular method for selecting the compensation compo-

nents is to create Bode plots of gain and phase for the power

stage and error amplifier. Combined, they make the overall

bandwidth and phase margin of the regulator easy to see.

Software tools such as Excel, MathCAD, and Matlab are

useful for showing how changes in compensation or the

power stage affect system gain and phase.

The power stage modulator provides a DC gain A

DC that is

equal to the input voltage divided by the peak-to-peak value

of the PWM ramp. This ramp is 1.0V

pk-pk for the LM2747.

The inductor and output capacitor create a double pole at

frequency f

DP, and the capacitor ESR and capacitance cre-

ate a single zero at frequency f

ESR. For this example, with

IN = 3.3V, these quantities are:

In the equation for f

DP, the variable RL is the power stage

resistance, and represents the inductor DCR plus the on

resistance of the top power MOSFET. R

O is the output

voltage divided by output current. The power stage transfer

function G

PS is given by the following equation, and Figure

14 shows Bode plots of the phase and gain in this example.

a=LC

O(RO +RC)

b=L +C

O(RORL +RORC +RCRL)

c=R

O +RL

The double pole at 4.5 kHz causes the phase to drop to

approximately -130˚ at around 10 kHz. The ESR zero, at

20.3 kHz, provides a +90˚ boost that prevents the phase

from dropping to -180o. If this loop were left uncompensated,

the bandwidth would be approximately 10 kHz and the

phase margin 53˚. In theory, the loop would be stable, but

would suffer from poor DC regulation (due to the low DC

gain) and would be slow to respond to load transients (due to

the low bandwidth.) In practice, the loop could easily become

unstable due to tolerances in the output inductor, capacitor,

or changes in output current, or input voltage. Therefore, the

loop is compensated using the error amplifier and a few

passive components.

For this example, a Type III, or three-pole-two-zero approach

gives optimal bandwidth and phase.

In most voltage mode compensation schemes, including

Type III, a single pole is placed at the origin to boost DC gain

20150964

FIGURE 13. Power Stage and Error Amp

20150969

20150970

FIGURE 14. Power Stage Gain and Phase

16SP100M Datasheet(PDF) 16 Page - National Semiconductor (TI)

16SP100M Datasheet(HTML) 16 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Datasheet Download

Link URL