TSC695F datasheet(13/42 Pages) ATMEL

13 / 42 page

TSC695F

4118H–AERO–06/03

Test and Diagnostic

Hardware Functions

A variety of TSC695F test and diagnostic hardware functions, including boundary scan,

internal scan, clock control and On-chip Debugger, are controlled through an IEEE

1149.1 (JTAG) standard Test Access Port (TAP).

Test Access Port

The TAP interfaces to the JTAG bus via 5 dedicated pins on the TSC695F chip. These

pins are:

•

TCK (input): Test Clock

•

TMS (input): Test Mode Select

•

TDI (input): Test Data Input

•

TDO (output): Test Data Output

•

TRST (input): Test Reset

Instruction Register

Five standard instructions are supported by the TSC695F TAP.

Debugging

The design is highly testable with the support of an On-Chip Debugger (OCD), an inter-

nal and boundary scan through JTAG interface.

Binary Value

Name of Instruction

Data Register

Scan Chain Accessed

00. 0000

EXTEST

Boundary Scan

Boundary scan chain

00. 0001

SAMPLE/PRELOAD

Boundary Scan

Boundary scan chain

00. 0011

INTEST

Boundary Scan

Boundary scan chain

11. 1111

BYPASS

Bypass Register

Bypass register

10. 0000

IDCODE

Device ID Register

ID register scan chain

TSC695F Datasheet(PDF) 13 Page - ATMEL Corporation

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