LTM4658EVPBF datasheet(15/26 Pages) AD

15 / 26 page

LTM4658

Rev. 0

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3. θJCtop, the thermal resistance from junction to top of

the product case, is determined with nearly all of the

component power dissipation flowing through the top

of the package. As the electrical connections of the

typical µModule are on the bottom of the package, it

is rare for an application to operate such that most of

the heat flows from the junction to the top of the part.

As in the case of θJCbottom, this value may be useful

for comparing packages but the test conditions don’t

generally match the user’s application.

A graphical representation of the aforementioned ther-

mal resistances is given in Figure 5; blue resistances are

contained within the µModule regulator, whereas green

resistances are external to the µModule.

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters defined by JESD51-12 or provided in the Pin

Configuration section replicates or conveys normal op-

erating conditions of a μModule. For example, in normal

board-mounted applications, never does 100% of the

device’s total power loss (heat) thermally conduct exclu-

sively through the top or exclusively through bottom of the

µModule—asthestandarddefinesforθJCtopandθJCbottom,

respectively.Inpractice,powerlossisthermallydissipated

in both directions away from the package—granted, in the

absence of a heat sink and airflow, a majority of the heat

flow is into the board.

Within a SIP (system-in-package) module, be aware there

are multiple power devices and components dissipating

power, with a consequence that the thermal resistances

relative to different junctions of components or die are not

exactly linear with respect to total package power loss. To

reconcile this complication without sacrificing modeling

simplicity—but also, not ignoring practical realities—an

approach has been taken using FEA software modeling

along with laboratory testing in a controlled-environment

chamber to reasonably define and correlate the thermal

resistance values supplied in this data sheet: (1) Initially,

FEA software is used to accurately build the mechanical

geometry of the µModule and the specified PCB with all

of the correct material coefficients along with accurate

power loss source definitions; (2) this model simulates

a software-defined JEDEC environment consistent with

JESD51-9 to predict power loss heat flow and temperature

readingsatdifferentinterfacesthatenablethecalculationof

theJEDEC-definedthermalresistancevalues;(3)themodel

and FEA software is used to evaluate the µModule with

heat sink and airflow; (4) having solved for and analyzed

these thermal resistance values and simulated various

operating conditions in the software model, a thorough

laboratory evaluation replicates the simulated conditions

with thermocouples within a controlled-environment

chamber while operating the device at the same power

loss as that which was simulated. An outcome of this

process and due-diligence yields a set of derating curves

provided in other sections of this data sheet.

APPLICATIONS INFORMATION

4658 F05

µModule DEVICE

θJCtop JUNCTION-TO-CASE

(TOP) RESISTANCE

θJA JUNCTION-TO-AMBIENT RESISTANCE

CASE (TOP)-TO-AMBIENT

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

θJCbot JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

JUNCTION

AMBIENT

CASE (BOTTOM)-TO-BOARD

RESISTANCE

Figure 5. Graphical Representation of JESD51-12 Thermal Coefficients

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