MAX77801 datasheet(21/31 Pages) MAXIM

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Operating in high-speed mode requires some special

considerations. For the full list of considerations, refer to

the I2C 3.0 specification. The major considerations with

respect to the MAX77801 are:

● I2C bus master uses current source pullups to

shorten the signal rise times.

● I2C slave must use a different set of input filters

on its SDA and SCL lines to accommodate for the

higher bus speed.

● The communication protocols need to utilize the

high-speed master code.

At power-up and after each STOP condition, the

MAX77801 input filters are set for standard mode, fast

mode, or fast mode plus (i.e., 0Hz to 1MHz). To switch

the input filters for high-speed mode, use the high-

speed master code protocols that are described in the

Communication Protocols section.

Communication Protocols

The MAX77801 supports both writing and reading from

its registers. The following sections show the I2C com-

munication protocols for each functional block. The power

block uses the same communications protocols.

Writing to a Single Register

Figure 13 shows the protocol for I2C master device to

write one byte of data to the MAX77801. This protocol is

the same as SMBus specification’s write byte protocol.

The write byte protocol is as follows:

1. The master sends a START command.

2. The master sends the 7-bit slave address followed by

a write bit (R/W 0).

3. The addressed slave asserts an ACKNOWLEDGE by

pulling SDA low.

4. The master sends an 8-bit register pointer.

5. The slave acknowledges the register pointer.

6. The master sends a data byte.

7. The slave acknowledges the data byte. At the rising

edge of SCL, the data byte will be loaded into its tar-

get register and the data becomes active.

8. The master sends a STOP condition or a REPEATED

START condition. Issuing a STOP ensures that the

bus input filters are set for 1MHz or slower operation.

Issuing a REPEATED START leaves the bus input

filters in their current state.

Writing to a Sequential Register

Figure 14 shows the protocol for writing to a sequential

registers. This protocol is similar to the write byte proto-

col, except the master continues to write after it receives

the first byte of data. When the master is done writing,

it issues a STOP or REPEATED START. The writing to

sequential registers protocol is as follows:

1. The master sends a START command.

2. The master sends the 7-bit slave address followed by

a write bit (R/W = 0).

3. The addressed slave asserts an ACKNOWLEDGE by

pulling SDA low.

4. The master sends an 8-bit register pointer.

5. The slave acknowledges the register pointer.

6. The master sends a data byte.

7. The slave acknowledges the data byte. At the rising

edge of SCL, the data byte will be loaded into its tar-

get register and the data becomes active.

8. Steps 6 to 7 are repeated as many times as the

master requires. During the last acknowledge related

clock pulse, the slave can issue an ACKNOWLEDGE.

9. The master sends a STOP condition or a REPEATED

START condition. Issuing a STOP ensures that the

bus input filters are set for 1MHz or slower operation.

Issuing a REPEATED START leaves the bus input

filters in their current state.

MAX77801

5.5V Input, 2A, High-Efficiency

Buck-Boost Converter

www.maximintegrated.com

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