ADP2126 datasheet(4/20 Pages) AD

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ADP2126/ADP2127

Data Sheet

Rev. B | Page 4 of 20

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

TIMING

See Figure 2 and Figure 3

VIN High to EXTCLK On2

VIN = 2.1 V to 5.5 V

200

μs

EXTCLK On to VOUT Rising

t2 (CLOCK)

DEXTCLK = 40% to 60%, fEXTCLK = 6 MHz

250

320

400

μs

DEXTCLK = 40% to 60%, fEXTCLK = 27 MHz

250

320

400

μs

EXTCLK On to VOUT Rising

t2 (LOGIC)

EXTCLK = logic high

285

315

385

μs

VOUT Power-Up Time (Soft Start)2

COUT = 2.2 μF, RLOAD = 3.6 Ω

200

μs

EXTCLK Off to VOUT Falling

t5 (CLOCK)

DEXTCLK = 40% to 60%, fEXTCLK = 6 MHz to 27 MHz

μs

EXTCLK Off to VOUT Falling

t5 (LOGIC)

EXTCLK = logic high, no load

μs

VOUT Power-Down Time

COUT = 2.2 μF, RLOAD = 3.6 Ω

μs

COUT = 2.2 μF, no load

465

μs

Minimum Shutdown Time2

t5 + t6

COUT = 2.2 μF, no load

1400

μs

Minimum Power-Off Time2

500

μs

1 The total shutdown current is the addition of VIN shutdown current and SW leakage.

2 Guaranteed by design.

3 Transients not included in voltage accuracy specifications.

4 The PFM output voltage will be higher than the PWM output voltage. See the Typi

section.

cal Performance Characteristics

5 Thermal shutdown protection is only active in PWM mode.

TIMING DIAGRAMS

VOUT(NOM) × 10%

VIN × 10%

VIN × 90%

VIN

VOUT

EXTCLK

Figure 2. Clock Enable I/O Timing Diagram

VOUT(NOM) × 10%

VIN × 10%

VIN × 90%

VIN

VOUT

EXTCLK

Figure 3. Logic Enable I/O Timing Diagram (Logic High Enable Feature Available Only on Certain Models)

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