SML2120 datasheet(18/32 Pages) SUMMIT

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I2C Interface

SML2120

2066 6.3 1/22/04

Summit Microelectronics

–

I2C INTERFACE

The I2C bus is a standard two-wire serial communication

interface used between different integrated circuits. The

two lines are serial data (SDA), which is a bi-directional pin,

and serial clock (SCL). The SML2120 supports a 100kHz

and 400kHz clock rate.

The SDA line must be connected to a positive supply by a

pull-up resistor located on the bus. The SML2120 contains

a Schmitt input on both the SDA and SCL signals.

When the slave address is 1001 and address bit 8 is low,

the Status register is accessed. When bit 8 is high, the A/D

converter is read. The channel read from the ADC is deter-

mined by the word address (see Figure 18).

When the slave address is 1010 and address bit 8 is low, the

General Purpose E2PROM is accessed. When bit 8 is high,

the Configuration registers are accessed.

When the slave address is 1011, address bit 8 determines

whether Lookup Table 0 or 1 is accessed. If bit 8 is ‘0’,

Lookup Table 0 is accessed. A ‘1’ accesses Lookup Table 1.

See Figure 23 and 24.

Start and Stop Conditions

Both the SDA and SCL pins remain high when the bus is not

busy. Data transfers between devices may be initiated with

a Start condition only when SCL and SDA are high. A high-

to-low transition of the SDA while the SCL pin is high is

defined as a Start condition. A low-to-high transition SDA

while SCL is high is defined as a Stop condition. Figure 11

shows a timing diagram of the start and stop conditions.

Figure 11. Start and Stop Conditions

Master/Slave Protocol

The master/slave protocol defines any device that sends

data onto the bus as a transmitter, and any device that

receives data as a receiver. The device controlling data

transmission is called the Master, and the controlled device

is called the Slave. In all cases the SML2120 is referred to

as a Slave device since it never initiates any data transfers.

Acknowledge

Data is always transferred in bytes. Acknowledge (ACK) is

used to indicate a successful data transfer. The transmitting

device releases the bus after transmitting eight bits. During

the ninth clock cycle the Receiver pulls the SDA line low to

acknowledge that it received the eight bits of data. This is

shown by the ACK callout in Figure 12.

When the last byte has been transferred to the Master

during a read of the SML2120, the Master leaves SDA high

for a Not Acknowledge (NACK) cycle. This causes the

SML2120 part to stop sending data, and the Master issues

a Stop on the clock pulse following the NACK.

Figure 12 shows the Acknowledge timing.

Figure 12. Acknowledge Timing

Read and Write

The first byte from a Master is always made up of a 7-bit

Slave address and the Read/Write (R/W) bit. The R/W bit

tells the Slave whether the Master is reading data from the

bus or writing data to the bus (1 = Read, 0 = Write). The first

four of the seven address bits are called the Device Type

Identifier (DTI). The DTI for the SML2120 is 1010BIN.

The next three bits are Address values for A2, A1, and A0

(if multiple devices are used). In the SML2120, A0 functions

as address bit 8. Refer to Table 4 for more information on

the state of address bit 8 and the access types supported.

The SML2120 issues an Acknowledge after recognizing a

Start condition. Figure 13 shows an example of a typical

master address byte transmission.

2050 Fig10 2.0

SCL

SDA In

START

Condition

STOP

Condition

SCL

SDA

Trans

SDA

Rec

ACK

2050 Fig11

SML2120 Datasheet(PDF) 18 Page - Summit Microelectronics, Inc.

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