SML2120 datasheet(19/32 Pages) SUMMIT

19 / 32 page

SML2120

Summit Microelectronics

2066 6.3 1/22/04

Figure 13. Typical Master Address Byte Transmission

During a read by the Master device, the SML2120 transmits

eight bits of data, then releases the SDA line, and monitors

the line for an Acknowledge signal. If an Acknowledge is

detected, and no Stop condition is generated by the Master,

the SML2120 continues to transmit data. If an Acknowledge

is not detected (NACK), the SML2120 terminates any

subsequent data transmission. The read transfer protocol

on SDA is shown in Figure 14.

Figure 14. Read Protocol

During a Master write, the SML2120 receives eight bits of

data, then generates an Acknowledge signal. It device

continues to generate the ACK condition on SDA until a

Stop condition is generated by the Master. The write transfer

protocol on SDA is shown in Figure 15.

Figure 15. Write Protocol

Random Access Read

Random address read operations allow the Master to

access any memory location in a random fashion. This

operation involves a two-step process. First, the Master

issues a Write command which includes the Start condition

and the Slave address field (with the R/W bit set to Write)

followed by the address of the word it is to read. This

procedure sets the internal address counter of the SML2120

to the desired address.

After the word address Acknowledge is received by the

Master, it immediately reissues a Start condition followed by

another Slave address field with the R/W bit set to Read.

The SML2120 responds with an Acknowledge and then

transmits the 8 data bits stored at the addressed location. At

this point, the Master sets the SDA line to NACK and

generates a Stop condition. The SML2120 discontinues

data transmission and reverts to its standby power mode.

Sequential Reads

Sequential reads can be initiated as either a current address

read or a random access read. The first word is transmitted

as with the other byte Read modes (current address byte

Read or random address byte Read). However, the Master

now responds with an Acknowledge, indicating that it

requires additional data from the SML2120.

The SML2120 continues to output data for each

Acknowledge received. The Master sets the SDA line to

NACK and generates a Stop condition. During a sequential

Read

operation

the

internal

address

counter

automatically incremented with each Acknowledge signal.

For Read operations all address bits are incremented,

allowing the entire array to be read using a single Read

command. After a count of the last memory address the

address counter rolls over and the memory continues to

output data.

Transaction Types

The figures below show timing diagrams for the following

transaction types.

• Status Register Read

• Status Register Write

• ADC Read

• Configuration E2PROM Read

• Configuration E2PROM Write

• General Purpose E2PROM Read

• General Purpose E2PROM Write

• Lookup Table Read

• Lookup Table Write

SCL

SDA

R/W

ACK

2050 Fig12

Master

SDA

Slave

1 0

xx x R xx x xx x xx

2050 Fig13

Master

SDA

Slave

1 0

xx x W

xx x xx x xx

2050 Fig14

SML2120 Datasheet(PDF) 19 Page - Summit Microelectronics, Inc.

SML2120 Datasheet(HTML) 19 Page - Summit Microelectronics, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL