PQ25181DLHT datasheet(21/43 Pages) TI

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The /INT pin is normally in high impedance and is pulled low for 128 μs when an interrupt condition occurs.

When a fault or status change occurs or any other condition that generates an interrupt, a 128-μs pulse (/INT pin

pulled down) is sent on /INT to notify the host.

Interrupts can be masked through I2C. If the interrupt condition occurs while the interrupt is masked an interrupt

pulse will not be sent. If the interrupt is unmasked while the fault condition is still present, an interrupt pulse

will not be sent until the /INT trigger condition occurs while unmasked. Below are a list of interrupts that can be

masked through I2C.

Table 8-6. Mask Bit

MASK BIT

ACTION

ILIM_INT_MASK

Do not issue an /INT pulse when ILIM limiting occurs

VDPM_INT_MASK

Do not issue an /INT pulse when VINDPM or DDPM is active

TS_INT_MASK

Do not issue an /INT pulse when any of the TS events have occured.

TREG_INT_MASK

Do not issue an /INT pulse when TREG is actively reducing the current

PG_INT_MASK

Do not issue an /INT pulse when VIN meets VIN_PG condition

BAT_INT_MASK

Do not issue an /INT pulse when BATOCP or BUVLO event is triggered

CHG_STATUS_INT_MASK

Do not send an interrupt anytime there is a charging status change.

8.3.13 Power Good (/PG_GPO) Pin

The /PG_GPO pin is an open-drain output that by default indicates when a valid IN supply is present. It can also

be configured to be a general purpose output (GPO) controlled through I2C. Connect /PG_GPO to the desired

logic voltage rail using a 1-kΩ to 100-kΩ resistor, or use with an LED for visual indication.

Below is the description for each configuration:

• In its default state, /PG_GPO pulls to GND when the following conditions are met: VIN > VINUVLO, VIN >

VBAT+VSLEEP and VIN < VIN_OVP. /PG_GPO is high impedance when the input power is not within specified

limits. PG_Mode is set to b0 to indicate the state of VIN.

• General purpose open drain output when setting the PG_MODE bits to b1. The state of the /PG_GPO pin is

then controlled through the PG_GPO bit, where if PG_GPO is b0 , the /PG_GPO pin is high impedance and if

it is b1, the /PG_GPO pin is low.

8.3.14 External NTC Monitoring (TS)

8.3.14.1 TS Biasing and Function

The device can be configured to meet JEITA requirements or a simpler HOT/COLD function only. Additionally,

the TS charger control function can be disabled through the TS_EN bit. This will only disable the TS charge

action but the faults are still reported based on the TS voltage. To satisfy the JEITA requirements, four

temperature thresholds are monitored: cold battery threshold, cool battery threshold, warm battery threshold,

and hot battery threshold. These temperatures correspond to the VCOLD, VCOOL, VWARM, and VHOT

thresholds in the Electrical Characteristics table. Charging and safety timers are suspended when VTS < VHOT

or VTS > VCOLD. When VCOOL < VTS < VCOLD, the charging current is reduced to the value programmed in the

TS_Setting register/bit TS_ICHG_0. When VHOT < VTS < VWARM, the battery regulation voltage is reduced by 100

mV or 200 mV based on the value programmed in the TS_VRCG_0 bit within the TS_Setting register.

For devices where the TS function is not needed, tie a 10-kΩ resistor to the TS pin.

There is an active voltage clamp present on this device which will prevent the voltage on the TSMR pin from

rising above the VTS_CLAMP threshold. This will particularly be ON when the TSMR pin is floating. The bit

TS_OPEN_STAT is set when this clamp is active. This will also be ON regardless of the TS_EN bit. The interrupt

is asserted as long as the TS_INT mask is not written.

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BQ25181

SLUSEH3 – APRIL 2022

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