LMK6P datasheet(9/42 Pages) TI

9 / 42 page

over the parameters listed in the Recommended Operating Conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tSTART_UP Start-up Time

Time elapsed from 0.95 × VDD until

output is enabled and output is within

specification

tOE-EN

Output Enable Time

Time elapsed from OE = VIH until

output is enabled and output is within

specification, Fout > 10 MHz

µs

tOE-DIS

Output Disable Time

Time elapsed from OE = VIL until output is

disabled, Fout > 10 MHz

µs

LVPECL - Clock Output Jitter

Random Phase Jitter

Fout ≥ 100 MHz, Integration BW: 12 kHz –

20 MHz

100

125

RJITT,RMS RMS Period Jitter

Fout ≥ 25 MHz

0.7

RJITT,PK

Peak-peak Period Jitter

Fout ≥ 25 MHz

LVDS - Clock Output Jitter

Random Phase Jitter

Fout ≥ 100 MHz, Integration BW: 12 kHz –

20 MHz

100

125

RJITT,RMS RMS Period Jitter

Fout ≥ 25 MHz

0.7

RJITT,PK

Peak-peak Period Jitter

Fout ≥ 25 MHz

LVCMOS - Clock Output Jitter

Random Phase Jitter

Fout = 24 MHz, Integration BW: 12 kHz –

5 MHz

400

Random Phase Jitter

Fout = 156.25 MHz, Integration BW: 12

kHz – 20 MHz

200

500

RJITT,RMS RMS Period Jitter

Fout ≥ 25 MHz

0.7

RJITT,PK

Peak-peak Period Jitter

Fout ≥ 25 MHz

(1)

Excluding Load current

(2)

DC Load condition

7.7 Timing Diagrams

VOD = VOH - VOL

OUTx_N

OUTx_P

VOUT-DIFF = 2 × VOD

0 V

20%

80%

VOH

VOL

Figure 7-1. Differential Output Voltage and Rise/Fall Time

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LMK6P, LMK6D, LMK6C

SNAS826 – APRIL 2022

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