MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order Number: MPC9993/D

Rev 1, 04/2003

1

Intelligent Dynamic Clock

Switch (IDCS) PLL Clock

Driver

The MPC9993 is a PLL clock driver designed specifically for redundant

clock tree designs. The device receives two differential LVPECL clock

signals from which it generates 5 new differential LVPECL clock outputs.

Two of the output pairs regenerate the input signals frequency and phase

while the other three pairs generate 2x, phase aligned clock outputs.

Features:

Functional Description

The MPC9993 Intelligent Dynamic Clock Switch (IDCS) circuit continuously monitors both input CLK signals. Upon detection

of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary

clock, the IDCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase

disturbance. The typical phase bump caused by a failed clock is eliminated. (See Application Information section).

Figure 1. Block Diagram

CLK0

CLK0

CLK1

CLK1

Ext_FB

Ext_FB

Sel_Clk

Dynamic Switch

Logic

PLL

PLL_En

÷8

÷16

Qb0

Qb0

Qb1

Qb1

Qb2

Qb2

Qa0

Qa0

Qa1

Qa1

MR

Man_Override

Clk_Selected

Inp1bad

Inp0bad

Alarm_Reset

OR

800 – 1600 MHz

MPC9993

FA SUFFIX

32–LEAD LQFP PACKAGE

CASE 873A