PCA8530DUGSLASHDAZ datasheet(74/103 Pages) NXP

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PCA8530

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Product data sheet

Rev. 2 — 25 September 2014

74 of 103

NXP Semiconductors

PCA8530

Automotive 102 x 4 Chip-On-Glass LCD segment driver

14.2 I2C-bus timing characteristics

[1]

tVD;DAT = minimum time for valid SDA output following SCL LOW.

[2]

tVD;ACK = time for acknowledgement signal from SCL LOW to SDA output LOW.

Table 50.

I2C-bus timing characteristic

VDD1, VDD2, VDD3 = 2.5 V to 5.5 V; VSS1 = 0 V; VLCD = 4.0 V to 12.0 V; Tamb = 40 C to +105 C; unless otherwise specified.

All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and

VIH with an input voltage swing of VSS1 to VDD1.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fSCL

SCL frequency

400

kHz

tBUF

bus free time between a

STOP and START

condition

1.3

s

tHD;STA

hold time (repeated)

START condition

0.6

s

tSU;STA

set-up time for a repeated

START condition

0.6

s

tVD;DAT

data valid time

[1] --

0.9

s

tVD;ACK

data valid acknowledge

time

[2] --

0.9

s

tLOW

LOW period of the SCL

clock

1.3

s

tHIGH

HIGH period of the SCL

clock

0.6

s

fall time

of both SDA and SCL

signals

0.3

s

rise time

of both SDA and SCL

signals

0.3

s

tSU;DAT

data set-up time

100

tHD;DAT

data hold time

tSU;STO

set-up time for STOP

condition

0.6

s

tw(spike)

spike pulse width

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