Data Sheet

ADM8323/ADM8324

Rev. B | Page 11 of 15

APPLICATIONS INFORMATION

WATCHDOG INPUT CURRENT

There is no way to disable the windowed watchdog functional-

ity. Do not leave the WDI pin floating because this is not a valid

mode of operation. If the WDI pin is not in a defined state at

startup, this can lead to high supply current until the microproces-

sor is enabled and takes control of the WDI pin. A solution to

this is to add a 100 kΩ pull-up or pull-down resistor on the

WDI pin to hold it in a defined state until the microprocessor

is enabled.

To avoid unnecessary resets caused by fast power supply transients,

the ADM8323/ADM8324 are equipped with glitch rejection

circuitry. The typical performance characteristic in Figure 14

curves show combinations of reset threshold overdrive and

duration for which a reset is not generated for 5 V, 4.63 V, and

2.93 V reset threshold devices. For example, with the 2.93 V

threshold, a transient that goes 100 mV below the threshold and

lasts 80 µs typically does not cause a reset. However, if the transient

is any larger in reset threshold overdrive or duration, a reset

generates. An optional 0.1 µF bypass capacitor mounted near

However, by using an external resistor with the push-pull

as low as 0 V is possible. For this active low reset output, a resistor

connected between RESET and ground pulls the output low

when it is unable to sink current. Use a large resistance, such as

is above 0.9 V.

ADM8323

RESET

100k

Ω

RESET

RESET

WDI

I/O

MR

MICROPROCESSOR

ADM8323

Figure 25. ADM8323 Typical Application Circuit