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DM9101
10/100Mbps Ethernet Physical Layer Single Chip Transceiver
20
Final
Version: DM9101-DS-F03
July 22, 1999
Register Description
Register Address
Register Name
Description
0
BMCR
Basic Mode Control Register
1
BMSR
Basic Mode Status Register
2
PHYIDR1
PHY Identifier Register #1
3
PHYIDR2
PHY Identifier Register #2
4
ANAR
Auto-Negotiation Advertisement Register
5
ANLPAR
Auto-Negotiation Link Partner Ability Register
6
ANER
Auto-Negotiation Expansion Register
16
DSCR
DAVICOM Specified Configuration Register
17
DSCSR
DAVICOM Specified Configuration/Status Register
18
10BTCSR
10Base-T Configuration/Status Register
Others
Reserved
Reserved For Future Use-Do Not Read/Write To These Registers
Key to Default
In the register description that follows, the default column takes the form:
<Reset Value>, <Access Type> / <Attribute(s)>
Where
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
(PIN#)
Value latched in from pin # at reset
<Access Type>:
RO = Read only
RW = Read/Write
<Attribute (s)>:
SC = Self clearing
P = Value permanently set
LL = Latching low
LH = Latching high
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