TI60 datasheet(21/70 Pages) ETC

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Ti60 Data Sheet

The HSIO supports the following I/O standards.

Table 6: HSIO Supported I/O Standards

VCCIO (V)

Standard

VCCAUX (V)

VREF (V)

When

Configured As

LVCMOS 1.8 V

1.8

–

GPIO

LVCMOS 1.5 V

1.5

1.8

–

GPIO

LVCMOS 1.2 V

1.2

1.8

–

GPIO

HSTL/Differential HSTL 1.8 V

SSTL/Differential SSTL 1.8 V

1.8

0.9

GPIO

HSTL/Differential HSTL 1.5 V

SSTL/Differential SSTL 1.5 V

1.5

1.5, 1.8(3)

1.8

0.75

GPIO

HSTL/Differential HSTL 1.2 V

SSTL/Differential SSTL 1.2 V

1.2

1.2, 1.5, 1.8(3)

1.8

0.6

GPIO

LVDS/RSDS/mini-LVDS

1.8

1.5, 1.8(3)

1.8

–

LVDS

Sub-LVDS

1.8

1.5, 1.8(3)

1.8

–

LVDS

MIPI Lane I/O /SLVS

1.2

1.8

–

MIPI Lane

The diﬀerential receivers are powered by VCCAUX, which gives you the ﬂexibility to

choose the VCCIO you want to use.

Features for HVIO and HSIO Configured as GPIO

The following table describes the features supported by HVIO and HSIO conﬁgured as

GPIO.

Table 7: Features for HVIO and HSIO Configured as GPIO

Feature

HVIO

HSIO

Configured

as GPIO

Double-data I/O (DDIO)

Dynamic pull-up

–

Pull-up/Pull-down

Slew-Rate Control

–

Variable Drive Strength

Schmitt Trigger

1:4 Serializer/Deserializer (Full rate mode only)

–

Programmable Bus Hold

–

Static Programmable Delay Chains

Dynamic Programmable Delay Chains

–

(3) To prevent pin leakage, you must ensure that the voltage at the pin does not exceed VCCIO.

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