TI60 datasheet(8/70 Pages) ETC

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Ti60 Data Sheet

DSP Block

The Titanium FPGA has high-performance, complex DSP blocks that can perform

multiplication, addition, subtraction, accumulation, and 4-bit variable right shifting. The 4-bit

variable right shift supports one lane in normal mode, two lanes in dual mode and four lanes

in quad mode. Each DSP block has four modes, which support the following multiplication

operations:

• Normal—One 19 x 18 integer multiplication with 48-bit addition/subtraction.

• Dual—One 11 x 10 integer multiplication and one 8 x 8 integer multiplication with two

24-bit additions/subtractions.

• Quad—One 7 x 6 integer multiplication and three 4 x 4 integer multiplications with four

12-bit additions/subtractions.

• Float—One fused-multiply-add/subtract/accumulate (FMA) BFLOAT16 multiplication.

The integer multipliers can represent signed or unsigned values based on the SIGNED

parameter. When multiple EFX_DSP12 or EFX_DSP24 primitives are mapped to the same

DSP block, they must have the same SIGNED value. The inputs to the multiplier are the

A and B data inputs. Optionally, you can use the result of the multiplier in an addition or

subtraction operation.

Figure 5: DSP Block Diagram

A[18:0]

B[17:0]

C[17:0]

Signed

pext

cext

OP[1:0]

CLK

RST

O[47:0]

Shift

CASCIN[47:0]

SHIFT_ENA

OVFL

CASCOUT[47:0]

DSP Block

Bypassable

1. Logical right-shift-by-18.

2. Arithmetic right-shift-by-18.

>> 18¹

>>> 18²

Learn more: Refer to the Quantum Titanium Primitives User Guide for more information about the

Titanium DSP block primitives.

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