AMC22C11 datasheet(8/43 Pages) TI

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6.9 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to 125°C, VDD1 = 3.0 V to 25 V, VDD2 = 2.7 V to 5.5 V, VREF =

20 mV to 2.7 V(1), and VIN = –400 mV to 4 V(2); typical specifications are at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V, and VREF

= 250 mV (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUT

RIN

Input resistance

IN pin, 0 ≤ VIN ≤ 4 V

GΩ

IBIAS

Input bias current

IN pin, 0 ≤ VIN ≤ 4 V(3)

0.1

IN pin, –400 mV ≤ VIN ≤ 0 V(4)

–310

–0.5

CIN

Input capacitance

IN pin

REFERENCE PIN

IREF

Reference current

REF to GND1, 20 mV < VREF ≤ 2.7 V

100

101

μA

VMSEL

Mode selection threshold

VREF rising

500

550

600

VREF falling

450

500

550

Mode selection threshold hysteresis

COMPARATOR

VIT+

Positive-going trip threshold

VREF + VHYS

EIT+

Positive-going trip threshold error

(VIT+ – VREF – VHYS),

VREF = 20 mV, VHYS = 4 mV

–2

(VIT+ – VREF – VHYS),

VREF = 250 mV, VHYS = 4 mV

–2

(VIT+ – VREF – VHYS),

VREF = 2 V, VHYS = 25 mV

–5

VIT–

Negative-going trip threshold

VREF

EIT–

Negative-going trip threshold error

(VIT– – VREF), VREF = 20 mV

–2.5

2.5

(VIT– – VREF), VREF = 250 mV

–2.5

2.5

(VIT– – VREF), VREF = 2 V

–5

VHYS

Trip threshold hysteresis

(VIT+ – VIT–), VREF ≤ 450 mV

(VIT+ – VIT–), VREF ≥ 600 mV

DIGITAL I/O

VIH

High-level input voltage

LATCH pin

0.7 x

VDD2

VDD2 +

0.3

VIL

Low-level input voltage

LATCH pin

–0.3

0.3 x

VDD2

CIN

Input capacitance

LATCH pin

VOL

Low-level output voltage

ISINK = 4 mA

250

ILKG

Open-drain output leakage current

VDD2 = 5 V, VOUT = 5 V

100

CMTI

Common-mode transient immunity

|VIN – VREF| ≥ 4 mV, RPULLUP = 10 kΩ

150

V/ns

AMC23C11-Q1

SBASAJ7A – JUNE 2022 – REVISED AUGUST 2022

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