SLG46117 datasheet(2/91 Pages) RENESAS

2 / 91 page

000-0046117-113

Page 1 of 89

SLG46117

1.0 Overview

The SLG46117 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit

design by programming the one time Non-Volatile Memory (NVM) to configure the interconnect logic, the I/O Pins and the

macrocells of the SLG46117. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a

very small, low power single integrated circuit. The SLG46117 includes the following:

• Two Analog Comparators (ACMP)

• Voltage References (Vref)

• Four Combinatorial Look Up Tables (LUTs)

• Two 2-bit LUTs

• Two 3-bit LUTs

•

Seven Combination Function Macrocell

• Two Selectable DFF/Latch or 2-bit LUTs

• Two Selectable DFF/Latch or 3-bit LUTs

• One Selectable Pipe Delay or 3-bit LUT

•

Pipe Delay – 8 stage / 2 output

• One Selectable Counter/Delay or 4-bit LUT

• One Programmable Delay/ Deglitch Filter

•

Three Counter / Delay Generators (CNT/DLY)

• Three 8-bit counter/delays with external clock/reset

•

Four D Flip-Flop / Latches (DFF) (Part of Combination Function Macrocell)

•

Pipe Delay – 8 stage/2 output (Part of Combination Function Macrocell)

•

Trimmed RC Oscillator (RC OSC)

•

Power On Reset (POR)

•

One Bandgap

•

Soft-Start P-FET Power Switch

• Power Switch IDS: 1 A to 1.5 A

• Slew Rate Control

• VIN: 1.5 V to 5.5 V

• Integrated Discharge Resistor

• Low RDSON

•

28.5 m

Ω @ 5.5 V

•

36.4 m

Ω @ 3.3 V

•

44.3 m

Ω @ 2.5 V

•

60.8 m

Ω @ 1.8 V

•

77.6 m

Ω @ 1.5 V

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