AD5941BCPZ datasheet(44/134 Pages) AD

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AD5940/AD5941

Data Sheet

Rev. C | Page 44 of 134

HIGH SPEED DAC OUTPUT ATTENUATION OPTIONS

Scaling options to modify the output signal amplitude to the sensor

are present for the high speed DAC output. The output of the 12-bit

DAC string is ±300 mV before any attenuation or gain. At the

DAC output, there is a gain stage of 1 or 0.2. At the PGA stage,

there are gain options of 2 or 0.25. Table 29 describes the avail-

able gain options and the corresponding output voltage ranges.

HIGH SPEED DAC EXCITATION AMPLIFIER

Figure 25 illustrates the operation of the excitation amplifier and

its connection to the switch matrix. There are four inputs to the

excitation amplifier: DACP, DACN, positive (P), and negative

(N). The high speed DAC is a differential output DAC where the

positive and negative inputs feed directly to the excitation amplifier.

Figure 25. High Speed DAC Excitation Amplifier

The voltage difference between these two outputs sets the peak-

to-peak voltage on the output waveform. The P and N inputs

maintain the stability of the excitation amplifier by providing a

feedback path from the sensor, and set the common-mode for

the high speed DAC output. Under normal circumstances, the

common mode is set by the VZERO0 output connected to the N

input. There is also an option to apply a dc bias voltage to the

sensor and couple an ac signal onto this bias, as shown in Figure

26.

Figure 26. Sensor Excitation Signal

An option is available if the sensor requires a bias voltage between

the counter and sense electrode. VBIAS0 sets the voltage on the

counter electrode (the common-mode voltage of the high speed

DAC) and VZERO0 sets the voltage on the sense electrode. VZERO0

must be connected to the positive terminal on the high speed TIA

(HSTIACON, Bits[1:0] = 01). The dc buffers of the DAC must

also be enabled by setting AFECON, Bit 21. With this configura-

tion, a waveform can be achieved, as shown in Figure 26. The

bias across the sensor is effectively the difference between VBIAS0

and VZERO0.

Note that the high speed DAC signal chain must never be used

in conjunction with the low power TIA. The high speed DAC

can become unstable, leading to incorrect measurements.

COUPLING AN AC SIGNAL FROM THE HIGH SPEED

DAC TO THE DC LEVEL SET BY THE LOW POWER

DAC

The AD5940/AD5941 contain a low power potentiostat channel

to configure an electrochemical sensor. In normal operation, the

bias voltage of the sensor between the RE0 and SE0 electrodes is

set by the low power DAC outputs, VBIAS0 and VZERO0, where VBIAS0

sets the bias to the potentiostat and the voltage on the CE0 pin.

VZERO0 sets the bias voltage on the low power TIA and the SE0 pin.

The high speed DAC circuit is not used. However, for ac

impedance measurements, the output of the excitation amplifier

must be connected to the CE0 pin. The potentiostat must be

disconnected so that the entire signal comes from the excitation

amplifier output. The high speed TIA is connected to the SE0 pin

and the low power TIA is disconnected. The sensor bias must then

be set by the high speed TIA and the excitation amplifier.

To set the sensor bias, take the following steps:

1. The VZERO0 output of the low power DAC must be connected

to the noninverting input of the high speed TIA (HSTIACON,

Bits[1:0] = 01), which sets the voltage on the SE0 pin, or

whichever pin is connected to the inverting input of the

high speed TIA via the switch matrix.

2. The DAC dc buffers must be enabled (AFECON, Bit 21 = 1).

Figure 25 shows the connection of the dc buffers to the

excitation amplifier. These buffers enable the low power

DAC outputs to drive the required bias voltage to the

excitation amplifier and the high speed TIA.

3. The dc bias is the difference between VBIAS0 and VZERO0.

AVOIDING INCOHERENCY ERRORS BETWEEN

EXCITATION AND MEASUREMENT FREQUENCIES

DURING IMPEDANCE MEASUREMENTS

The following settings are recommended to avoid incoherency

errors between excitation and measurement frequencies during

impedance measurements:

•

The Hanning window is always on (DFTCON Bit 0 = 1).

•

In low power mode, the high speed DAC update rate is

16 MHz ÷ 7 (HSDACCON Bits[8:1] = 0x1B). In high power

mode, the high speed DAC update rate is 32 MHz ÷ 7

(HSDACCON Bits[8:1] = 0x7).

•

In low power mode, the ADC sampling rate is 800 kSPS

(high frequency oscillator = 16 MHz). In high power

mode, the ADC sampling rate is 1.6 MSPS (high frequency

oscillator = 32 MHz).

Note that disabling the Hanning window may result in

degraded performance.

–

PGA

12-BIT

DAC

RCF

DACP

DACN

–

VBIAS0_PIN

VZERO0_PIN

DAC DC BUFFERS

AFECON[21]

VZERO0

BIAS VOLTAGE

(UP TO 600mV)

VBIAS0

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