AD5941BCPZ datasheet(58/134 Pages) AD

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AD5940/AD5941

Data Sheet

Rev. C | Page 58 of 134

Bits

Bit Name

Settings

Description

Reset

Access

[13:12]

SINC3OSR

Sinc3 filter oversampling rate.

0x0

R/W

Oversampling rate of 5. Use this setting for the 160 kHz sinc3 filter output

update rate and when the ADC update rate is 800 kSPS (default).

Oversampling rate of 4. Use this setting for the 400 kHz sinc3 filter output

update rate and when the ADC update rate is 1.6 MSPS. High power option.

Oversampling rate of 2. Use this setting for the 400 kHz sinc3 filter output

update rate and when the ADC update rate is 800 kSPS.

Oversampling rate of 5. Use this setting for the 160 kHz sinc3 filter output

update rate and when the ADC update rate is 800 kSPS.

[11:8]

SINC2OSR

Sinc2 oversampling rate (OSR).

0x3

R/W

22 samples for this OSR setting.

44 samples for this OSR setting.

89 samples for this OSR setting.

178 samples for this OSR setting.

100

267 samples for this OSR setting.

101

533 samples for this OSR setting.

110

640 samples for this OSR setting.

111

667 samples for this OSR setting.

1000

800 samples for this OSR setting.

1001

889 samples for this OSR setting.

1010

1067 samples for this OSR setting.

1011

1333 samples for this OSR setting.

AVRGEN

ADC average function enable. The average output feeds directly to the DFT

block and, when this bit is set, the DFT source automatically changes to the

average output.

0x0

R/W

Disable average.

Enable average to feed to the DFT block.

SINC3BYP

Sinc3 filter bypass. This bit bypasses the sinc3 filter.

0x0

R/W

Sinc3 filter enable.

Bypasses the sinc3 filter. Raw 800 kHz or1.6 MHz ADC output data is fed directly

to the gain offset adjustment stage. If the sinc3 filter is bypassed, the 200 kHz

sine wave can be handled directly by the DFT block without amplitude

attenuation. If the sinc3 filter is bypassed and the ADC raw data rate is 800 kHz,

the gain offset block output is used as the DFT input.

Reserved

0x0

LPFBYPEN

50 Hz/60 Hz low-pass filter.

0x0

R/W

Enables the 50 Hz/60 Hz notch filter. The ADC result is written to the

SINC2DAT register.

Bypasses the 50 Hz notch and 60 Hz notch filters.

[3:1]

Reserved

Reserved.

0x0

ADCSAMPLERATE

ADC data rate. Unfiltered ADC output rate.

0x0

R/W

800 kHz.

1.6 MHz. If the ADC sample rate = 1.6 MHz, the ACLK frequency to analog

must be 32 MHz (refer to the clock configuration).

ADC Raw Result Register—ADCDAT

Address 0x00002074, Reset: 0x00000000, Name: ADCDAT

The ADCDAT register is the ADC result register for the raw ADC output or when the sinc3 and/or sinc2 filter options are selected.

Table 44. Bit Descriptions for ADCDAT Register

Bits

Bit Name

Settings

Description

Reset

Access

[31:16]

Reserved

Reserved.

0x0

[15:0]

Data

ADC result. This register contains the ADC conversion result. Depending on the user

configuration, this result can reflect raw, sinc3, or sinc2 filter outputs. This result is a

16-bit unsigned number.

0x0

R/W

AD5941BCPZ Datasheet(PDF) 58 Page - Analog Devices

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