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MPFS250T Datasheet(PDF) 38 Page - Microchip Technology |
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MPFS250T Datasheet(HTML) 38 Page - Microchip Technology |
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38 / 50 page ![]() 5. System Controller The PolarFire SoC FPGA system controller is based on the industry-standard ARM Cortex-M3 and is used for FPGA power-up, secure DPA-safe FPGA programming, and executing and responding to system services. All internal memories are SECDED-protected with background scrubbing capabilities to remove single-bit errors. 5.1 System Services System services provide the user with information about the state of the FPGA and allow the user to request the system controller to perform predefined functions using a standard Application Programming Interface (API). The system services are listed as follows. Design Services • Initialize fabric RAM • Bitstream authentication • IAP image authentication Device Services • Serial number • JTAG user code • Design version number • Device certificate Data Services • sNVM read/write • PUF emulation service • Nonce service FPGA Fabric Services • Digest check • In-application programming 5.2 Programming PolarFire SoC FPGAs have multiple programming modes designed to enable various use models. All bitstreams are always encrypted and DPA safe. Each PolarFire SoC FPGA can be programmed using a dedicated SPI peripheral and JTAG port. All PolarFire SoC FPGAs are typically reprogrammed in less than 60 seconds. For device specific programming timings, see the PolarFire SoC FPGA Datasheet. The following programming modes are supported: Slave Programming • JTAG • Slave SPI—an external SPI master programs the FPGA SPI Master Programming—In-Application Programming (IAP) • Auto update feature—the system controller on power-up checks for a new bitstream in an external SPI flash and programs the FPGA. • Auto programming feature—on a blank device, the system controller on power-up checks for a bitstream in an external SPI flash and programs the FPGA. • Programming recovery feature—if remote programming fails due to a power interruption, the system controller reprograms the FPGA on the next power-up cycle from a golden bitstream (located in an external SPI flash). System Controller © 2021 Microchip Technology Inc. and its subsidiaries Overview DS60001656C-page 38 |
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