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2.5

Digital Audio Interface (J40)

2.6

Control Interface (J30)

Digital Audio Interface (J40)

The digital audio interface contains digital audio signal data (I2S), clocks etc. Please see

TAS5508 data manual for signal timing and details not explained in this document.

Table 2-5. J40 Pin Description

PIN NUMBER

NET-NAME AT SCHEMATICS

DESCRIPTION

1

GND

Ground

2

MCLK

Master Clock input. Low jitter system clock for

PWM generation and reclocking. Ground connec-

tion from source to TAS5508 must be a low

impedance connection.

3

GND

Ground

4

SDIN1

I2S Data 1, Channel 1 and 2

5

SDIN2

I2S Data 2, Channel 3 and 4

6

SDIN3

I2S Data 3, Channel 5 and 6

7

SDIN4

I2S Data 4, Channel 7 and 8

8

-

Reserved

9

-

Reserved

10

GND

Ground

11

SCLK

I2S bit clock.

12

GND

Ground

13

LRCLK

I2S left-right clock

14

GND

Ground

15

-

Reserved

16

GND

Ground

This interface connects the TAS5508-5122C6EVM board to a TI input board.

Table 2-6. J40 Pin Description

PIN NUMBER

NET-NAME AT SCHEMATICS

DESCRIPTION

1

GND

Ground

2

-

Reserved

3

GND

Ground

4

/RESET

System reset (bi-directional). Activate MUTE before

RESET for quiet reset

5

/BKND_ERR

Backend error (or soft reset) provides reduced click

and pop reset, without resetting I2C volume regis-

ter settings

6

/MUTE

Ramp volume from any setting to noiseless soft

mute. Mute can also be activated by I2C

7

/PDN

Power down. TAS5508 will go to power down state

when activated

8

-

Reserved

9

-

Reserved

10

SDA

I2C data clock

11

GND

Ground

12

SCL

I2C bit clock

System Interfaces

14

SLEU058 – October 2004