HT36F6 datasheet(13/37 Pages) HOLTEK

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HT36F6

Rev. 1.00

August 15, 2005

Timer 0/1

Timer 0 is an 8-bit counter, and its clock source comes

from the system clock divided by an 8-stage prescaler.

There are two registers related to Timer 0; TMR0L(0DH)

and TMR0C(0EH). One physical registers are mapped

to TMR0L location; writing TMR0L makes the starting

value be placed in the Timer 0 preload register and

reading the TMR0 gets the contents of the Timer 0 coun-

ter. The TMR0C is a control register, which defines the

division ration of the prescaler and counting enable or

disable.

Writing data to B2, B1 and B0 (bits 2, 1, 0 of TMR0C)

can yield various clock sources.

One the Timer 0 starts counting, it will count from the

current contents in the counter to FFH. Once an over-

flow occurs, the counter is reloaded from a preload reg-

ister, and generates an interrupt request flag (T0F; bit 2

of INTCH). To enable the counting operation, the timer

On bit (TON; bit 4 of TMR0C) should be set to

²1². For

proper operation, bit 7 of TMR0C should be set to

²1²

and bit 3, bit 6 should be set to

²0².

There are two registers related to the Timer Counter1;

TMR1L(10H), TMR1C(11H). The Timer Counter 1 oper-

ates in the same manner as Timer Counter 0.

TMR0C/TMR1C

T0F

SYS CLK/16

SYS CLK/32

SYS CLK/64

SYS CLK/128

SYS CLK/256

SYS CLK/512

SYS CLK/1024

SYS CLK/2048

TMR0C Bit 4 to enable/disable timer counting

(1=enable; 0=disable)

TMR0C Bit 3, always write

²0².

TMR0C Bit 5, always write

²0².

TMR0C Bit 6, always write

²0².

TMR0C Bit 7, always write

²1².

Input/Output Ports

There are 20 bidirectional input/output lines labeled

from PA, PB, PC0~PC3, which are mapped to the data

memory of [12H], [14H], [16H] respectively. All these I/O

ports can be used for input and output operations. For

input operation, these ports are non-latching, that is, the

inputs must be ready at the T2 rising edge of instruction

MOV A,[m] (m=12H, 14H or 16H). For output operation,

all data is latched and remains unchanged until the out-

put latch is rewritten.

Each I/O line has its own control register (PAC, PBC,

PCC0~PCC3) to control the input/output configuration.

With this control register, CMOS output or Schmitt trig-

ger input with or without pull-high resistor (mask option)

structures can be reconfigured dynamically under soft-

ware control. To function as an input, the corresponding

latch of the control register must write a

²1². The

pull-high resistance will exhibit automatically if the

pull-high option is selected. The input source also de-

pends on the control register. If the control register bit is

²1², input will read the pad state. If the control register bit

²0², the contents of the latches will move to the internal

bus. The latter is possible in

²read-modify-write² instruc-

tion. For output function, CMOS is the only configura-

tion. These control registers are mapped to locations

13H, 15H and 17H.

After a chip reset, these input/output lines remain at high

levels or floating (mask option). Each bit of these in-

put/output latches can be set or cleared by the

²SET

[m].i

² or ²CLR [m].i² (m=12H, 14H or 16H) instruction.

Some instructions first input data and then follow the

output operations. For example, the

²SET [m].i², ²CLR

[m].i

², ²CPL [m]² and ²CPLA [m]² instructions read the

entire port states into the CPU, execute the defined op-

erations (bit-operation), and then write the results back

to the latches or the accumulator. Each line of port A has

the capability to wake-up the device.

S y s t e m

C l o c k / 8

8 - s t a g e

P r e s c a l e r

T i m e r 0 / 1

P r e l o a d R e g i s t e r

T i m e r 0 / 1

D a t a B u s

R e l o a d

O v e r f l o w

T O N

T 0 F

Timer 0/1

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