HT49CV7 datasheet(11/48 Pages) HOLTEK

11 / 48 page

HT49RV7/HT49CV7

Rev. 1.00

April 20, 2006

Interrupts

The HT49RV7/HT49CV7 provides two external inter-

rupts, two internal timer/event counter interrupts, three

remote control timer interrupts, an internal real time

clock interrupt and serial interface interrupt. The inter-

rupt control register 0 (INTC0;0BH) and interrupt control

bits that are used to set the enable/disable status and in-

terrupt request flags.

Once an interrupt subroutine is serviced, all other inter-

rupts are blocked (by clearing the EMI bit). This scheme

may prevent any further interrupt nesting. Other inter-

rupt requests may take place during this interval, but

only the interrupt request flag will be recorded. If another

interrupt requires servicing while the program is in the

interrupt service routine, the programmer should set the

EMI bit and the corresponding bit of the INTC0 or INTC1

to allow interrupt nesting. Once the stack is full, the inter-

rupt request will not be acknowledged, even if the related

interrupt is enabled, until the SP is decremented. If imme-

diate service is desired, the stack should be prevented

from becoming full.

All these interrupts can support a wake-up function. As

an interrupt is serviced, a control transfer occurs by push-

ing the contents of the Program Counter onto the stack

followed by a branch to a subroutine at the specified loca-

tion in the ROM. Only the contents of the Program Coun-

ter is pushed onto the stack. If the contents of the register

or of the status register (STATUS) is altered by the inter-

rupt service program which corrupts the desired control

sequence, the contents should be saved in advance.

External interrupts are triggered by an edge transition of

INT0 or INT1 (configuration option: high to low, low to

high, low to high or high to low), and the related interrupt

request flag (EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0)

is set as well. After the interrupt is enabled, the stack is

not full, and the external interrupt is active, a subroutine

call to location 04H or 08H occurs. The interrupt request

flag (EIF0 or EIF1) and EMI bits are all cleared to disable

other maskable interrupts.

The internal Timer/Event Counter 0 interrupt is initial-

ized by setting the Timer/Event Counter 0 interrupt re-

quest flag (T0F; bit 6 of INTC0), which is normally

caused by a timer overflow. After the interrupt is en-

abled, and the stack is not full, and the T0F bit is set, a

subroutine call to location 0CH occurs. The related inter-

rupt request flag (T0F) is reset, and the EMI bit is

cleared to disable other maskable interrupts.

Timer/Event Counter 1 is operated in the same manner

but its related interrupt request flag is T1F (bit 4 of

INTC1) and its subroutine call location is 10H.

The Serial Interface interrupt is initialized by setting the

interrupt request flag (TDRF; bit 5 of INTC1), which is

caused by completely receiving or transferring 8 bits of

data from a serial interface. After the interrupt is en-

abled, and the stack is not full, and the TRF bit is set, a

subroutine call to location 14H occurs. The related inter-

rupt request flag (TDRF) is reset and the EMI bit is

cleared to disable further maskable interrupts.

The multi-function interrupt is initialized by setting the in-

terrupt request flag (MFF; bit 6 of INTC1), which is

caused by a regular real time clock signal, or caused by

a rising edge of RMT, or caused by a falling edge of

RMT, or caused by an RMT overflow. After the interrupt

is enabled, and the stack is not full, and the MFF bit is

set, a subroutine call to location 18H occurs. The related

interrupt request flag (MFF) is reset and the EMI bit is

cleared to disable further maskable interrupts.

During the execution of an interrupt subroutine, other

maskable interrupt acknowledgments are all held until

the

²RETI² instruction is executed or the EMI bit and the

related interrupt control bit are both set to 1 (if the stack

is not full). To return from the interrupt subroutine,

²RET²

²RETI² may be invoked. RETI sets the EMI bit and en-

ables an interrupt service, but RET does not.

Interrupts occurring in the interval between the rising

edges of two consecutive T2 pulses are serviced on the

latter of the two T2 pulses if the corresponding interrupts

are enabled. In the case of simultaneous requests, the

following table shows the priority that is applied. These

can be masked by resetting the EMI bit.

Interrupt Source

Priority

Vector

External interrupt 0

04H

External interrupt 1

08H

Timer/Event Counter 0 overflow

0CH

Timer/Event Counter 1 overflow

10H

Serial Interface interrupt

14H

Multi-function interrupt

18H

The RMT overflow interrupt flag (RMTVF; bit 0 of MFIS),

real time clock interrupt flag (RTF; bit 1 of MFIS), the

RMT rising edge interrupt flag (RMT0F; bit 2 of MFIS)

and the RMT falling edge interrupt flag (RMT1F; bit 3 of

MFIS) indicate that a related interrupt has occurred. Af-

ter reading these flags, these flags will not be cleared

automatically, they should be cleared by the user.

The serial interface interrupt is indicated by the interrupt

flag (TDRF; bit 5 of INTC1), that is caused by receiving

or transferring a complete 8-bit data transfer between

the HT49RV7/HT49CV7 and an external device. After

the interrupt is enabled (by setting ESBI; bit 1 of INTC1),

and the stack is not full, a subroutine call to location 14H

occurs. TDRF is set by SIO and should be cleared by

users. (Only at the later stage will the INTC bit-5 TDRF

specs be released, while the SBCR bit-0 TRF specs re-

main as is.)

The Timer/Event Counter 0 interrupt request flag (T0F),

external interrupt 1 request flag (EIF1), external inter-

rupt 0 request flag (EIF0), enable Timer/Event Counter0

HT49CV7 Datasheet(PDF) 11 Page - Holtek Semiconductor Inc

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