MN89302

For Information Equipment

Pin Descriptions

Pin No.

Symbol

I/O

Level

Function Description

27

AEN

I

TTL

Address Enable

"H" level input from this pin indicates that a DMA transfer is in

progress, so the chip does not respond to I/O access.

28

SBHE

I

TTL

Byte High Enable

This input indicates the state of the 16-bit bus.

24

IOWR

I

TTL

I/O Write

This input indicates an I/O write request.

25

IORD

I

TTL

I/O Read

This input indicates an I/O read request.

22

SMEMW

I

TTL

Memory Write

This input indicates a memory write request dedicated for an

address space in the first megabyte (000000 to 0FFFFFH).

16

SMEMR

I

TTL

Memory Read

This input indicates a memory read request dedicated for an

address space in the first megabyte (000000 to 0FFFFFH).

6 to 5

A[21:20]

I

TTL

Address[21:20]

These inputs give the address 21:20.

4 to 1,

SA[19:0]

I

TTL

Address[19:0]

128 to 115,

These inputs give the address 19:0.

21 ,39

30 to 48

SD[15:0]

I/O

TTL

Data[15:0]

These pins represent the host data bus.

23

IOCHRDY

I/O

TTL

I/O Channel Ready

This pin is "L" level when I/O or memory access is given wait

states.

19

MEMCS16

O

TTL

Memory Chip Select 16

This output indicates to the system that 16-bit memory access is

available.

18

IOCS16

O

TTL

I/O Chip Select 16

This output indicates to the system that 16-bit I/O access is

available.

15

REFRESH

I

TTL

Refresh

"L" level input indicates that the system is refreshing its DRAM.

89 to 80

MA[9:0]

I/O

CMOS

Memory Address

These outputs give the address of the display memory .

91

RAS

O

CMOS

Row Address Strobe (RAS).

This output is the strobe signal for the row address latch.

93

UCAS

O

CMOS

Upper Column Address Strobe (UCAS)

This output is the strobe signal for the upper column address

latch. In the 2WE mode, however, it functions as the CAS

signal.