HT48C10 datasheet(31/59 Pages) HOLTEK

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Mnemonic

Description

Flag Affected

Instruction

Cycle

Miscellaneous

NOP

CLR [m]

SET [m]

CLR WDT

CLR WDT1

CLR WDT2

SWAP [m]

SWAPA [m]

HALT

No operation

Clear data memory

Set data memory

Clear Watchdog timer

Pre-clear Watchdog timer

Swap nibbles of data memory

Swap nibbles of data memory with result in ACC

Enter power down mode

None

TO,PD

TO*,PD*

None

TO,PD

(1)

Notes: x: 8-bit immediate data

m: 7-bit data memory address for HT48C10/HT48C30

m: 8-bit data memory address for HT48C50/HT48C70

A: Accumulator

i: 0~7 number of bits

A: Accumulator

i: 0~7 number of bits

addr: Program memory address

√: Flag(s) is affected

–: Flag(s) is not affected

*: Flag(s) may be affected by the execution status

(1): If a loading to PCL register occurs, the execution cycle of the instructions will be delayed

one more cycle (4 system clocks).

(2): If a skip to next instruction occurs, the execution cycle of instructions will be delayed one

more cycle (4 system clocks). Otherwise the original execution cycles remain unchanged.

(3) : (1) or (2)

HT48CXX/HT48RXX

25th May ’99

HT48C10 Datasheet(PDF) 31 Page - Holtek Semiconductor Inc

HT48C10 Datasheet(HTML) 31 Page - Holtek Semiconductor Inc

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