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LM4901MM Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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LM4901MM Datasheet(HTML) 5 Page - National Semiconductor (TI) |
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5 / 24 page ![]() Electrical Characteristics V DD = 2.6V (Notes 1, 2) The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for T A = 25˚C. (Continued) Note 12: All bumps have the same thermal resistance and contribute equally when used to lower thermal resistance. The LM4901IBL demo board (views featured in the Application Information section) has two inner layers, one for VDD and one for GND. The planes each measure 611mils x 661mils (15.52mm x 16.79mm) and aid in spreading heat due to power dissipation within the IC. Note 13: Maximum power dissipation in the device (PDMAX) occurs at an output power level significantly below full output power. PDMAX can be calculated using Equation 1 shown in the Application Information section. It may also be obtained from the power dissipation graphs. Note 14: The Exposed-DAP of the LDA10B package should be electrically connected to GND or an electrically isolated copper area. the LM4901LD demo board (views featured in the Application Information section) has the Exposed-DAP connected to GND with a PCB area of 86.7mils x 585mils (2.02mm x 14.86mm) on the copper top layer and 550mils x 710mils (13.97mm x 18.03mm) on the copper bottom layer. Note 15: The thermal performance of the LLP package (LM4901LD) when used with the exposed-DAP connected to a thermal plane is sufficient for driving 4 Ω loads. The LM4901LD demo board (views featured in the Application Information section) can drive 4 Ω loads at the maximum power dissipation point (1.267W) without thermal shutdown circuitry being activated. The other available packages (MSOP & micro SMD) do not have the thermal performance necessary for driving 4 Ω loads with a 5V supply and are not recommended for this application. External Components Description (Figure 1) Components Functional Description 1. R i Inverting input resistance which sets the closed-loop gain in conjunction with R f. This resistor also forms a high pass filter with C i at fC= 1/(2 π R iCi). 2. C i Input coupling capacitor which blocks the DC voltage at the amplifiers input terminals. Also creates a highpass filter with R i at fc = 1/(2 π R iCi). Refer to the section, Proper Selection of External Components, for an explanation of how to determine the value of C i. 3. R f Feedback resistance which sets the closed-loop gain in conjunction with R i. 4. C S Supply bypass capacitor which provides power supply filtering. Refer to the Power Supply Bypassing section for information concerning proper placement and selection of the supply bypass capacitor. 5. C B Bypass pin capacitor which provides half-supply filtering. Refer to the section, Proper Selection of External Components, for information concerning proper placement and selection of C B. Typical Performance Characteristics THD+N vs Frequency at V DD = 5V, 8 Ω R L, and PWR = 500mW THD+N vs Frequency at V DD = 3V, 8 Ω R L, and PWR = 250mW 20019830 20019831 www.national.com 5 |
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