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U637256
5
March 31, 2006
STK Control #ML0054
Rev 1.0
Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = VIH)
f
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)
g
No.
Switching Characteristics
Write Cycle
Symbol
Min.
Max.
Unit
Alt. #1
Alt. #2
IEC
12 Write Cycle Time
tAVAV
tAVAV
tcW
70
ns
13 Write Pulse Width
tWLWH
tw(W)
55
ns
14 Write Pulse Width Setup Time
tWLEH
tsu(W)
55
ns
15 Address Setup Time
tAVWL
tAVEL
tsu(A)
0ns
16 Address Valid to End of Write
tAVWH
tAVEH
tsu(A-WH)
55
ns
17 Chip Enable Setup Time
tELWH
tsu(E)
55
ns
18 Chip Enable to End of Write
tELEH
tw(E)
55
ns
19 Data Setup Time to End of Write
tDVWH
tDVEH
tsu(D)
30
ns
20 Data Hold Time after End of Write
tWHDX
tEHDX
th(D)
0ns
21 Address Hold after End of Write
tWHAX
tEHAX
th(A)
0ns
22 W LOW to Output in High-Zh, i
tWLQZ
tdis(W)
25
ns
23 W HIGH to Output in Low-Z
tWHQX
ten(W)
5ns
ta(A)
Previous Data Valid
Output Data Valid
tcR
Address Valid
tv(A)
Ai
DQi
Output
(1)
(2)
(9)
Ai
E
G
tdis(E)
tcR
ta(E)
ten(E)
ten(G)
ta(G)
tdis(G)
Address Valid
Output Data Valid
ICC
ACTIVE
STANDBY
tPD
tPU
(1)
(3)
(4)
(5)
(7)
(6)
(8)
(10)
(11)
ta(A) (2)
High Impedance
DQi
Output
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