U637256
1
March 31, 2006
STK Control #ML0054
Rev 1.0
CapStore 32K x 8 nvSRAM
Pin Configuration
Pin Description
Top View
1
A14
VCC
28
2
A12
W
27
4
A6
A8
25
5
A5
A9
24
3
A7
A13
26
6
A4
A11
23
7
A3
G
22
8
A2
A10
21
12
DQ1
DQ5
17
9
A1
E
20
10
A0
DQ7
19
11
DQ0
DQ6
18
13
DQ2
DQ4
16
14
VSS
DQ3
15
PDIP
Signal Name
Signal Description
A0 - A14
Address Inputs
DQ0 - DQ7
Data In/Out
E
Chip Enable
G
Output Enable
W
Write Enable
VCC
Power Supply Voltage
VSS
Ground
The U637256 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U637256 is a static RAM with
a nonvolatile electrically erasable
PROM (EEPROM) element incor-
porated in each static memory cell.
The SRAM can be read and written
an unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in an integraed
capacitor.
Transfers
from
the
EEPROM
to
the
SRAM
(the
RECALL
operation)
take
place
automatically on power up. The
U637256 combines the ease of use
of an SRAM with nonvolatile data
integrity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
The U637256 is pin compatible
with standard SRAMs and standard
battery backed SRAMs.
Features
Description
CMOS non volatile static RAM
32768 x 8 bits
70 ns Access Time
35 ns Output Enable Access
Time
ICC = 15 mA typ. at 200 ns Cycle
Time
Unlimited Read and Write Cycles
to SRAM
Automatic STORE to EEPROM
on Power Down using charge
stored in an integrated capacitor
Software initiated STORE
Automatic STORE Timing
106 STORE cycles to EEPROM
100 years data retention in
EEPROM
Automatic RECALL on Power Up
Software RECALL Initiation
Unlimited RECALL cycles from
EEPROM
Single 5 V
± 10 % Operation
Operating temperature range:
0 to 70
°C
-40 to 85
°C
QS 9000 Quality Standard
(MIL STD 883C M3015.7)
RoHS compliance and Pb- free
Package: PDIP28 (600 mil)
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