DS320PR810 datasheet(4/38 Pages) TI

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Table 5-1. Pin Functions

TYPE(1)

DESCRIPTION

NAME

NO.

ALL_DONE_N

O, 3.3 V open

drain

In SMBus/I2C Primary mode:

Indicates the completion of a valid EEPROM register load operation. External pullup

resistor such as 4.7 kΩ required for operation.

High: External EEPROM load failed or incomplete

Low: External EEPROM load successful and complete

In SMBus/I2C Secondary/Pin mode:

This output is High-Z. The pin can be left floating.

MODE

I, 5-level

Sets device control configuration modes. 5-level IO pin as provided in Table 7-4. The

pin can be exercised at device power up or in normal operation mode.

L0: Pin mode – device control configuration is done solely by strap pins.

L1: SMBus/I2C Primary mode – device control configuration is read from external

EEPROM. When the DS320PR810 has finished reading from the EEPROM

successfully, it will drive the ALL_DONE_N pin LOW. SMBus/I2C secondary operation

is available in this mode before, during or after EEPROM reading. Note: during

EEPROM reading if the external SMBus/I2C primary wants to access DS320PR810

registers it must support arbitration.

L2: SMBus/I2C Secondary mode – device control configuration is done by an external

controller with SMBus/I2C primary.

L3 and L4 (Float): RESERVED – TI internal test modes.

EQ0 / ADDR0

I, 5-level

In Pin mode:

Sets receiver linear equalization (CTLE) boost for channels 0-3 (Bank 0) as provided in

Table 7-1. These pins are sampled at device power-up only.

In SMBus/I2C mode:

Sets SMBus / I2C secondary address as provided in Table 7-5. These pins are

sampled at device power-up only.

EQ1 / ADDR1

I, 5-level

EQ0_1

I, 5-level

Sets receiver linear equalization (CTLE) boost for channels 4-7 (Bank 1) as provided in

Table 7-1 in Pin mode. The pin is sampled at device power-up only.

EQ1_1

I, 5-level

GAIN0 / SDA

I, 5-level / I/O,

3.3 V

LVCMOS,

open drain

In Pin mode:

Flat gain (DC and AC) from the input to the output of the device for channels 0-3 (Bank

0). The pin is sampled at device power-up only.

In SMBus/I2C mode:

3.3 V SMBus/I2C data. External 1 kΩ to 5 kΩ pullup resistor is required as per SMBus /

I2C interface standard.

GAIN1

I, 5-level

Flat gain (DC and AC) from the input to the output of the device for channels 4-7 (Bank

1) in Pin mode. The pin is sampled at device power-up only.

GND

EP, 9, 12, 21,

24, 32, 41, 44,

53, 56, 64

Ground reference for the device.

EP: the Exposed Pad at the bottom of the QFN package. It is used as the GND return

for the device. The EP should be connected to one or more ground planes through the

low resistance path. A via array provides a low impedance path to GND. The EP also

improves thermal dissipation.

PD0

I, 3.3 V

LVCMOS

2-level logic controlling the operating state of the redriver. Active in all device control

modes. The pin has internal 1-MΩ weak pull-down resistor. The pin triggers PCIe Rx

detect state machine when toggled.

High: power down for channels 0-3

Low: power up, normal operation for channels 0-3

PD1

I, 3.3 V

LVCMOS

2-level logic controlling the operating state of the redriver. Active in all device control

modes. The pin has internal 1-MΩ weak pull-down resistor. The pin triggers PCIe Rx

detect state machine when toggled.

High: power down for channels 4-7

Low: power up, normal operation for channels 4-7

READ_EN_N

I, 3.3 V

LVCMOS

In SMBus/I2C Primary mode:

After device power up, when the pin is low, it initiates the SMBus / I2C Primary mode

EEPROM read function. When EEPROM read is complete (indicated by assertion of

ALL_DONE_N low), this pin can be held low for normal device operation. During the

EEPROM load process the device’s signal path is disabled.

In SMBus/I2C Secondary and Pin modes:

In these modes the pin is not used. The pin can be left floating. The pin has internal

1-MΩ weak pull-down resistor.

RSVD0

—

Reserved use for TI. The pin must be left floating (NC).

DS320PR810

SNLS668 – AUGUST 2022

www.ti.com

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