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DS320PR810 Datasheet(PDF) 19 Page - Texas Instruments |
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DS320PR810 Datasheet(HTML) 19 Page - Texas Instruments |
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19 / 38 page ![]() Table 7-7. EEPROM_Status Register (Offset = 0xE3) Bit Field Type Reset Description 7 eecfg_cmplt R 0x0 EEPROM load complete. 6 eecfg_fail R 0x0 EEPROM load failed. 5 eecfg_atmpt_1 R 0x0 Number of attempts made to load EEPROM image. 4 eecfg_atmpt_0 R 0x0 see MSB 3 eecfg_cmplt R 0x0 EEPROM load complete 2. 2 eecfg_fail R 0x0 EEPROM load failed 2. 1 eecfg_atmpt_1 R 0x0 Number of attempts made to load EEPROM image 2. 0 eecfg_atmpt_0 R 0x0 see MSB Table 7-8. DEVICE_ID0 Register (Offset = 0xF0) Bit Field Type Reset Description 7-4 RESERVED R 0x0 Reserved 3 device_id0_3 R 0x0 Device ID0 [3:1]: 011 2 device_id0_2 R 0x1 see MSB 1 device_id0_1 R 0x1 see MSB 0 RESERVED R X Reserved Table 7-9. DEVICE_ID1 Register (Offset = 0xF1) Bit Field Type Reset Description 7 device_id[7] R 0x0 Device ID 0010 1001: DS320PR810 6 device_id[6] R 0x0 see MSB 5 device_id[5] R 0x1 see MSB 4 device_id[4] R 0x0 see MSB 3 device_id[3] R 0x1 see MSB 2 device_id[2] R 0x0 see MSB 1 device_id[1] R 0x0 see MSB 0 device_id[0] R 0x0 see MSB 7.5.2.2 Channel Registers Table 7-10. RX Detect Status Register (Channel register base + Offset = 0x00) Bit Field Type Reset Description 7 rx_det_comp_p R 0x0 Rx Detect positive data pin status: 0: Not detected 1: Detected – the value is latched 6 rx_det_comp_n R 0x0 Rx Detect negative data pin status: 0: Not detected 1: Detected – the value is latched 5-0 RESERVED R 0x0 Reserved Table 7-11. EQ Gain Control Register (Channel register base + Offset = 0x01) Bit Field Type Reset Description 7 eq_stage1_bypass R/W 0x0 Enable EQ stage 1 bypass: 0: Bypass disabled 1: Bypass enabled www.ti.com DS320PR810 SNLS668 – AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: DS320PR810 |
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