TMUX7436F datasheet(32/47 Pages) TI

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Both the FF pin and the SF pin are an open-drain output and an external pull-up resistor of 1 kΩ is

recommended. The pull-up voltage can be in the range of 1.8 V to 5.5 V, depending on the controller voltage the

device interfaces with.

8.3.4 Bidirectional Operation

The TMUX7436F conducts equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx).

However, it is noted that the overvoltage protection is implemented only on the source (Sx) side. The voltage on

the drain is only allowed to swing between VDD and VSS and no overvotlage protection is available on the drain

side.

The flatest on-resistance region extends from VSS to roughly 3 V below VDD. Once the signal is within 3 V of VDD

the on-resistance will expoentially increase and may impact desired signal transmission.

8.3.5 1.8 V Logic Compatible Inputs

The TMUX7436F device has 1.8 V logic compatible control for all logic control inputs. 1.8 V logic level inputs

allows the TMUX7436F to interface with processors that have lower logic I/O rails and eliminates the need for an

external translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations,

refer to Simplifying Design with 1.8 V logic Muxes and Switches.

8.3.6 Integrated Pull-Down Resistor on Logic Pins

The TMUX7436F has internal weak pull-down resistors to GND to ensure the logic pins are not left floating. The

value of this pull-down resistor is approximately 4 MΩ, but is clamped to about 1 µA at higher voltages. This

feature integrates up to four external components and reduces system size and cost.

8.4 Device Functional Modes

The TMUX7436F offers two modes of operation (normal mode and fault mode) depending on whether any of the

input pins experience an overvoltage condition.

8.4.1 Normal Mode

In Normal mode operation, signals of up to VDD and VSS can be passed through the switch from source (Sx) to

drain (Dx) or from drain (Dx) to source (Sx). As provided in Table 8-1, the select pins (SELx) and enable pin (EN)

determines which switch path to turn on. The following conditions must be satisfied for the switch to stay in the

ON condition:

• The difference between the supples (VDD – VSS) must be greater than or equal to 8 V, with a minimum VDD of

5 V.

• The input signals on the source (Sx) or the drain (Dx) must be be between VDD+ VT and VSS – VT.

• The logic control (SELx and EN) must have selected the switch.

8.4.2 Fault Mode

The TMUX7436F enters into Fault mode when any of the input signals on the source (Sx) pins exceed VDD

or VSS by a threshold voltage VT. Under the overvoltage condition, the switch input experiencing the fault

automatically turns off regardless of the logic status, and the source pin becomes high impedance with negligible

amount of leakage current flowing through the switch. For more information about how the drain pain (Dx)

behavior under the Fault mode can be programmed, see Section 8.3.2.4.

In the Fault mode, the general fault flag (FF) is asserted low. Table 8-1 provides how the specific flag (SF) is

asserted low depending on the status of the logic control pins SELx and EN.

The overvoltage protection is provided only for the source (Sx) input pins. The drain (Dx) pin, if used as signal

input, must stay in between VDD and VSS at all times since no overvoltage protection is implemented on the drain

pin.

TMUX7436F

SCDS459 – OCTOBER 2022

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