3

SP8720

OPERATING NOTES

1. The clock input is biased internally and is coupled to the signal

source with a suitable capacitor. The input signal path is completed

by an input reference decoupling capacitor which is connected

from pin 16 to ground.

2. If no signal is present the device will self-oscillate. If this is

undesirable, it may be prevented by connecting a 15k

Ω resistor

sensitivity by approximately 100mV.

3. The circuit will operate down to DC but slew rate must be better

than 100V/

µs.

4. The Q and Q outputs are compatible with ECLII but can be

interfaced to ECL10K as shown in Fig. 7. There is an internal

circuit equivalent to a load of 2k

Ω at each output.

5. The PE inputs are ECLIII/10K compatible and include 4·3k

Ω

pulldown resistors. Unused inputs can therefore be left open.

6. The input impedance of the SP8720 varies as a function of

frequency, see Fig. 5.

7. All components should be suitable for the frequency in use.

Fig. 5 Typical input impedance. Test conditions: Supply Voltage = 25·2V,

Ambient Temperature = 25

°C. Frequencies in MHz, impedances normalised to 50Ω.

Fig. 6 Test circuit

DUT

450

450

100n

100n

OUTPUTS TO

SAMPLING

SCOPE

5

8

9

12

16

1

1n

1n

1n

33

33

20

INPUT FROM

GENERATOR

TO SAMPLING

SCOPE

150

j 2

j 1

j 0.5

j 0.2

0

2

j 0.2

2

j 0.5

2

j 1

2

j 2

1

0.5

0.2

j 5

2

j 5

2

5

100

200

300

250

50