L9963T datasheet(18/45 Pages) STMICROELECTRONICS

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VSPICLKFREQ [V] (typ.)

Vcode [3:0]

SCLK Frequency

Circuit malfunction

0100

250 kHz

VCLKTH2 ≤ VSPICLKFREQ < VCLKTH3

0011

4 MHz

Circuit malfunction

0010

250 kHz

VCLKTH1 ≤ VSPICLKFREQ < VCLKTH2

0001

1 MHz

VSPICLKFREQ < VCLKTH1

0000

250 kHz

Refer to Table 15 for the recommended selection of the external pull down resistor.

Table 15. Recommended components for SPI clock frequency selection in master mode

SCLK Frequency

Recommended RSPICLKFREQ [kΩ]

RSPICLKFREQ Tolerance [%]

250 kHz

Short to GND

1 MHz

9.31

4 MHz

16.2

8 MHz

22.9

The 4 analog comparators are BISTed during Trimming & Config Latch and, in case the BIST fails, the slowest

SCLK configuration is chosen (250 kHz).

MCU is supposed to implement a communication timeout mechanism able to detect slower than normal

communication bit rate.

The biasing current ISPICLKFREQPU, the comparators and voltage divider are disabled once Trimming &

Config Latch is left, in order to avoid unnecessary power consumption.

Figure 11. SPICLKFREQ pin structure

L9963T

Pin configuration

DS13590 - Rev 4

page 18/45

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