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L9963T Datasheet(PDF) 27 Page - STMicroelectronics |
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L9963T Datasheet(HTML) 27 Page - STMicroelectronics |
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27 / 45 page  Symbol Parameters Test conditions Min Typ Max Unit Note Tpcld Propagation delay (time passed after propagating SCK edge @ at SDO active) Cload = 60 pF Valid for SDO - - 30 ns 60% of ½ Tclk @ 10 MHz Tlead time passed after NCS H/L edge @ first SCK edge Application info 100 - - ns - Tscld SDI input setup time (time passed after SDI data valid @ sampling SCK edge) Application info 10 - - ns 20% of ½ Tclk @ 10 MHz Thcld SDI input hold time (time passed after propagating SCK edge @ SDI data “not valid anymore” ) Application info 10 - - ns 20% of ½ Tclk @ 10 MHz Tsclch Time passed after CLK -> CPOL @ NCS H/L edge FCLK_SPI = 10 MHz 75 - - ns - Tlag Time passed after CLK -> CPOL @ NCS L/H edge FCLK_SPI = 10 MHz 100 - - ns - Thclch CLK high after NCS high FCLK_SPI = 10 MHz 100 - - ns - Tonncs NCS min high time FCLK_SPI = 10 MHz 300 - - ns > 4 TMAIN_OSC max value (considering fMAIN_OSC = 15 MHz) Tpchdz NCS L/H to SDO @ high impedance FCLK_SPI = 10 MHz Cload = 60 pF - - 75 ns <<Tonncs Tcsdv NCS H/L to SDO active FCLK_SPI = 10 MHz Cload = 60 pF - - 75 ns - Parameters for L9963T SPI Master (NSLAVE = 1) FCLK_SPI CLK frequency (50% duty cycle) Design info 0.25 - 8 MHz Selectable among 250 kHz, 1 MHz, 4 MHz, 8 MHz Tcll Minimum time CLK = LOW FCLK_SPI = 8 MHz 58.6 62.5 - ns Considering 6.25% internal clock uncertainty FCLK_SPI = 4 MHz 117.2 125 - ns FCLK_SPI = 1 MHz 468.8 500 - ns FCLK_SPI = 250 kHz 1.88 2 - μs Tclh Minimum time CLK = HIGH FCLK_SPI = 8 MHz 58.6 62.5 - ns Considering 6.25% internal clock uncertainty FCLK_SPI = 4 MHz 117.2 125 - ns FCLK_SPI = 1 MHz 468.8 500 - ns FCLK_SPI = 250 kHz 1.88 2 - μs Tpcld Propagation delay (time passed after propagating SCK edge @ at SDO active) FCLK_SPI = 10 MHz Cload = 60 pF - - 25 ns 50% of ½ Tclk @ 10MHz (Constrained by Slave spec) Tlead CLK toggle after NCS = low FCLK_SPI = 8 MHz 1 - 1.51 μs Less important when CPHA = 1 because the first SPI data bit is propagated by the first SCK edge after the NCS low FCLK_SPI = 4 MHz 1 - 1.51 μs FCLK_SPI = 1 MHz 4 - 7.72 μs FCLK_SPI = 250 kHz 4 - 7.72 μs Tscld SDI input setup time (time passed after SDI data valid @ sampling SCK edge) FCLK_SPI = 10 MHz 10 - - ns 20% of ½ Tclk @ 10 MHz (Constrained by Slave spec) L9963T Serial communication interface DS13590 - Rev 4 page 27/45 |
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