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TDA75610DLVPD Datasheet(PDF) 28 Page - STMicroelectronics |
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TDA75610DLVPD Datasheet(HTML) 28 Page - STMicroelectronics |
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28 / 37 page ![]() I2C bus TDA75610DLVPD 28/37 DocID024175 Rev 8 9.3.2 Start and stop conditions As shown by Figure 38 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. 9.3.3 Byte format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 9.3.4 Acknowledge The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see Figure 39). The receiver** has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. * Transmitter – master (µP) when it writes an address to the TDA75610DLVPD – slave (TDA75610DLVPD) when the µP reads a data byte from TDA75610DLVPD ** Receiver – slave (TDA75610DLVPD) when the µP writes an address to the TDA75610DLVPD – master (µP) when it reads a data byte from TDA75610DLVPD Figure 37. Data validity on the I2C bus Figure 38. Timing diagram on the I2C bus Figure 39. Acknowledge on the I2C bus |
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