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AP63301 Datasheet(PDF) 15 Page - Diodes Incorporated

Part # AP63301
Description  3.8V TO 32V INPUT, 3A LOW IQ SYNCHRONOUS BUCK WITH ENHANCED EMI REDUCTION
PDF  22 Pages
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Manufacturer  DIODES [Diodes Incorporated]
Direct Link  http://www.diodes.com
Logo DIODES - Diodes Incorporated

AP63301 Datasheet(HTML) 15 Page - Diodes Incorporated

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AP63300/AP63301
Document number: DS42002 Rev. 3 - 2
15 of 22
www.diodes.com
August 2019
© Diodes Incorporated
AP63300/AP63301
Application Information (continued)
4
Electromagnetic Interference (EMI) Reduction with Ringing-Free Switching Node and Frequency Spread Spectrum (FSS)
In some applications, the system must meet EMI standards. In relation to high frequency radiation EMI noise, the switching node
’s (SW’s) ringing
amplitude is especially critical. To dampen high frequency radiated EMI noise, the AP63300/AP63301 device implements a proprietary, multi-level
gate driver scheme that achieves a ringing-free switching node without sacrificing the switching nod
e’s rise and fall slew rates as well as the
converter’s power efficiency.
To further improve EMI reduction, the AP63300 device also implements FSS with a switching frequency jitter of ±6%. FSS reduces conducted and
radiated interference at a particular frequency by spreading the switching noise over a wider frequency band and by not allowing emitted energy to
stay in any one frequency for a significant period of time.
5
Adjusting Undervoltage Lockout (UVLO)
Undervoltage lockout is implemented to prevent the IC from insufficient input voltages. The AP63300/AP63301 device has a UVLO comparator
that monitors the input voltage and the internal bandgap reference. The AP63300/AP63301 disables if the input voltage falls below 3.06V. In this
UVLO event, both the high-side and low-side power MOSFETs turn off.
For applications requiring higher VIN UVLO threshold voltages than is provided by the default setup, a 4µA hysteresis pull-up current source on
the EN pin along with an external resistive divider (R3 and R4) configures the VIN UVLO threshold voltages as shown in Figure 37.
VIN
R3
R4
ON
EN
1.18V
I1
1.5μA
I2
4μA
20kΩ
+
–
Figure 37. Programming UVLO
The resistive divider resistor values are calculated by:
Eq. 2
Eq. 3
Where:
VON is the rising edge VIN voltage to enable the regulator and is greater than 3.7V
VOFF is the falling edge VIN voltage to disable the regulator and is greater than 3.26V
6
Output Overvoltage Protection (OVP)
The AP63300/AP63301 implements output OVP circuitry to minimize output voltage overshoots during decreasing load transients. The high-side
power MOSFET turns off and the low-side power MOSFET turns on when the output voltage exceeds its target value by 10% in order to prevent
the output voltage from continuing to increase.



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