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MITSUBISHI

〈DIGITAL ASSP〉

M66252P/FP

1152 x 8-BIT LINE MEMORY (FIFO)

MITSUBISHI

〈DIGITAL ASSP〉

M66252P/FP

1152 x 8-BIT LINE MEMORY (FIFO)

PIN CONFIGURATION (TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

12

14

15

16

13

19

18

17

20

21

22

23

24

GND

RCK

WCK

Data output

Data output

Data input

Data input

24P4Y

24P2W-A

Outline

Read enable input

Read reset input

Read clock input

Write enable input

Write reset input

Write clock input

RE

RRES

WE

WRES

BLOCK DIAGRAM

24 23 22 21 16 15 14 13

Input buffer

1

234

9 10 11 12

Output buffer

20

19

17

18

Memory array

(1152 x 8 bits)

5

6

8

7

RE

RRES

RCK

GND

WE

WRES

WCK

Vcc

Write

enable input

Write

reset input

Write

clock input

Read

reset input

Read

enable input

Read

clock input

Data input

Data output

DESCRIPTION

The M66252P/FP is a high-speed line memory with a FIFO

(First In First Out) structure of 1152-word

× 8-bit configuration

which uses high-performance silicon gate CMOS process

technology.

It has separate clock, enable and reset signals for write and

read and is most suitable as a buffer memory between

devices with different data processing throughput.

FEATURES

• Memory construction ........................................................

............................. 1152words x 8bits (dynamic memory)

• High-speed cycle ............................................ 50ns (min.)

• High-speed access ........................................ 40ns (max.)

• Output hold ....................................................... 5ns (min.)

• Fully independent, asynchronous write and read opera-

tions

• Variable-length delay bit

• Output .................................................................... 3-state

APPLICATION

Digital photocopiers, high-speed facsimiles, laser beam print-

ers.