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EN5360DI Datasheet(PDF) 9 Page - Enpirion, Inc. |
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EN5360DI Datasheet(HTML) 9 Page - Enpirion, Inc. |
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9 / 11 page ![]() Rev 1.0 – July 2005 www.enpirion.com 9 EN5360 Power Up Sequencing The sequencing of AVIN, PVIN and ENABLE should meet the following requirements: 1. ENABLE should not be asserted before PVIN. 2. PVIN should not be applied before AVIN. Note that tying AVIN, PVIN and ENABLE together and brought up at the same time does meet these requirements. POK Operation The POK signal is an open drain signal from the converter indicating the output voltage is within the specified range. The POK signal will be a logic high when the output voltage is within 90% - 120% of the programmed output voltage. If the output voltage goes outside of this range, the POK signal will be a logic low until the output voltage has returned to within this range. In the event of an over-voltage condition the POK signal will go low and will remain in this condition until the output voltage has dropped to 95% of the programmed output voltage before returning to the high state (see also Over Voltage Protection) Over-Current Protection The cycle-by-cycle current limit function is achieved by sensing the current flowing through the sense P- MOSFET and a signal generated by a differential amplifier with a preset over-current threshold. During a particular cycle, if the over-current threshold is exceeded, the power P-MOSFET is turned off and the power N-MOSFET is turned on to protect the P- MOSFET. If the over-current condition is removed, the over-current protection circuit will enable the PWM operation. If the over-current condition persists, the converter will eventually go through a full soft- start cycle. This circuit is designed to provide high noise immunity. It is possible to raise the over-current set-point by ~50% by connecting a 4.99k Ω resistor between ROCP and GND. Over-Voltage Protection When the output voltage exceeds 120% of the programmed output voltage, the PWM operation stops, the lower N-MOSFET is turned on and the POK signal goes low. When the output voltage drops below 95% of the programmed output voltage, normal PWM operation resumes and POK returns to its high state. Thermal Overload Protection Thermal shutdown will disable operation once the Junction temperature exceeds approximately 160ºC. Once the junction temperature drops by approx 25ºC, the converter will re-start with a normal soft-start. Input Under-voltage Operation Circuitry is provided to ensure that when the input voltage is below the specified voltage range, the operation of the converter is controlled and predictable. Circuits for hysteresis, input de-glitch and output leading edge blanking are included to ensure high noise immunity and prevent false tripping. Compensation The EN5360 is internally compensated through the use of a type 3 compensation network and is optimized for use with about 50µF of output capacitance and will provide excellent loop bandwidth and transient performance for most applications. (See the section on Capacitor Selection for details on recommended capacitor types.) In some cases modifications to the compensation may be required. For more information, contact Enpirion Applications Engineering support. Layout Considerations The EN5360 Layout Guidelines application note provides more details on specific layout recommendations for this part. The following are general layout guidelines to consider. The CMOS chip inside the EN5360 has two grounds: AGND for the controller, and PGND for the power stage. These two grounds need to be connected outside the package at one point through a low- impedance trace. The connection should be made such that the impedance between the connection point and the AGND pad on the package is minimized. Since the internal voltage sensing circuit is based on AGND, the connection of the two grounds should also be made such that the best voltage regulation can be achieved. The soft-start capacitor, the voltage programming resistors, and any other external control component should be tied to AGND. The placement of the input decoupling capacitors and |
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