10

ICS950813

Advance Information

0708—10/10/02

Table 3

PCI_STOP# I

Note: When this Byte 0, Bit 3 is low (0), all PCI clocks are stopped.

Table 4

CPUCLKT/C (2:0) Outputs I

Note: Individual CPUCLK outputs are controlled by Byte 1, Bit 3, 4, and 5.

Table 5

PCICLK_F (2:0) Outputs I

Note: Individual PCICLK outputs are controlled by Byte 3, Bit 3, 4, and 5.

Table 6

3V66 (5:2) I

Note: Activating Byte 5, Bit 5 will allow CPU_STOP# to control stop of pins 21, 22, 23, and 24.

Table 7

3V66 (1:0) I

Note: Activating Byte 5, Bit 4 will allow CPU_STOP# to control stop of pins 33 and 35.

1

1

Running

0

1

Stopped

1

0

Running

3V66 (1:0)

0

0

Running

1

1

CPU_STOP#

(Pin 53)

Byte 5

Bit 4

Running

Running

0

0

0

1

Running

Stopped

1

0

1

0

Running

1

1

Running

0

0

Stop

0

1

Running

1

1

Running

PCI_STOP#

(Pin 34)

Byte 3

Bit 3, 4, 5

PCICLK (2:0) Outputs

0

1

Running

1

0

Running

CPUCLKT/C (2:0) Outputs

0

0

Stop

1

PCI_STOP#

(Pin 34)

CPU_STOP#

(Pin 53)

Byte 1

Bit 3, 4, 5

Byte 0 Bit 3

Write Bit

0

0

Byte 0, Bit 3 Read Bit

(Internal Status)

0

0

0

CPU_STOP#

(Pin 53)

Byte 5

Bit 5

3V66 (5:2)

0

1

1

0

1`

1