DM9000CIEP datasheet(14/63 Pages) DAVICOM

14 / 63 page

DM9000C/CI

Industrial-Temperature Ethernet Controller with General Processor Interface

Final

Version: DM9000C/CI-13-DS-F01

December 12, 2012

RSCCR

Resume System Clock Control Register

51H

XXH

MRCMDX

Memory Data Pre-Fetch Read Command Without Address

Increment Register

F0H

XXH

MRCMDX1

Memory Data Read Command With Address Increment

F1H

XXH

MRCMD

Memory Data Read Command With Address Increment

F2H

XXH

MRRL

Memory Data Read_ address Register Low Byte

F4H

00H

MRRH

Memory Data Read_ address Register High Byte

F5H

00H

MWCMDX

Memory Data Write Command Without Address Increment

F6H

XXH

MWCMD

Memory Data Write Command With Address Increment

F8H

XXH

MWRL

Memory Data Write_ address Register Low Byte

FAH

00H

MWRH

Memory Data Write _ address Register High Byte

FBH

00H

TXPLL

TX Packet Length Low Byte Register

FCH

XXH

TXPLH

TX Packet Length High Byte Register

FDH

XXH

ISR

Interrupt Status Register

FEH

00H

IMR

Interrupt Mask Register

FFH

00H

Key to Default

In the register description that follows, the default column

takes the form:

Where：

<Reset Value>:

Bit set to logic one

Bit set to logic zero

No default value

P = power on reset default value

S = software reset default value

E = default value from EEPROM

T = default value from strap pin

<Access Type>:

RO = Read only

RW = Read/Write

R/C = Read and Clear

RW/C1=Read/Write and Cleared by write 1

WO = Write only

Reserved bits are shaded and should be written with 0.

Reserved bits are undefined on read access.

*If Register 1FH bit 0 is updated from ‘1’ to ‘0’, the all Registers can not be accessed within 1ms.

6.1 Network Control Register (00H)

Bit

Name

Default

Description

RESERVED

P0,RW

Reserved

WAKEEN

P0,RW

When set, it enables the wakeup function. Clearing this bit will also clears all

wakeup event status

This bit will not be affected after a software reset

0: Enable

1: Disable

RESERVED

0,RO

Reserved

FCOL

PS0,RW

1: Force Collision Mode, used for testing

0: DISABLE

FDX

PS0,RO

Duplex mode of the internal PHY.

1: Full-duplex

0: half-duplex

DM9000CIEP Datasheet(PDF) 14 Page - Davicom Semiconductor, Inc.

DM9000CIEP Datasheet(HTML) 14 Page - Davicom Semiconductor, Inc.

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