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DM9000CIEP Datasheet(PDF) 21 Page - Davicom Semiconductor, Inc.

Part # DM9000CIEP
Description  DAVICOM Semiconductor, Inc.
PDF  63 Pages
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Manufacturer  DAVICOM [Davicom Semiconductor, Inc.]
Direct Link  http://www.davicom.com.tw
Logo DAVICOM - Davicom Semiconductor, Inc.

DM9000CIEP Datasheet(HTML) 21 Page - Davicom Semiconductor, Inc.

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DM9000C/CI
Industrial-Temperature Ethernet Controller with General Processor Interface
Final
21
Version: DM9000C/CI-13-DS-F01
December 12, 2012
6.11 RX/TX Flow Control Register ( 0AH )
Bit
Name
Default
Description
7
TXP0
PS0,RW
Force TX Pause Packet
Auto clears after pause packet transmission completion. Set to TX pause packet
with time = 0000h
6
TXPF
PS0,RW
Force TX Pause packet
Auto clears after pause packet transmission completion. Set to TX pause packet
with time = FFFFH
5
TXPEN
PS0,RW
TX Pause Packet Enable
Enables the pause packet for high/low water threshold control
1: ENABLE
0: DISABLE
4
BKPA
PS0,RW
Back Pressure Mode
This mode is for half duplex mode only. It generates a jam pattern when any
packet comes and RX SRAM is over BPHW of register 8.
1: ENABLE
0: DISABLE
3
BKPM
PS0,RW
Back Pressure Mode
This mode is for half duplex mode only. It generates a jam pattern when a packet’s
DA matches and RX SRAM is over BPHW of register 8.
1: ENABLE
0: DISABLE
2
RXPS
PS0,R/C
RX Pause Packet Status, latch and read clearly
1: has been receive pause packet
0: no pause packet received
1
RXPCS
PS0,RO
RX Pause Packet Current Status
1: received pause packet timer down-count in progress
0: pause packet timer value is zero
0
FLCE
PS0,RW
Flow Control Enable
Set to enable the flow control mode (i.e. can disable DM9000C/CI TX function)
1: ENABLE
0: DISABLE
6.12 EEPROM & PHY Control Register ( 0BH )
Bit
Name
Default
Description
7:6
RESERVED
0,RO
Reserved
5
REEP
P0,RW
Reload EEPROM. Driver needs to clear it up after the operation completes
4
WEP
P0,RW
Write EEPROM Enable
1: ENABLE
0: DISABLE
3
EPOS
P0,RW
EEPROM or PHY Operation Select
0: select EEPROM
1: select PHY
2
ERPRR
P0,RW
EEPROM Read or PHY Register Read Command. Driver needs to clear it up after
the operation completes.
1
ERPRW
P0,RW
EEPROM Write or PHY Register Write Command. Driver needs to clear it up after
the operation completes.



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