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©Copyright 2006. STATS ChipPAC Ltd. All rights reserved.

May 2006

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FLGA-SD

Fine Pitch Land Grid Array - Stacked Die

SPECIFICATIONS

Die Thickness

75–165µm (3-6.5 mils)

Mold Cap Thickness

0.45-0.9mm

Marking

Laser

Packing Options

Tape & reel/JEDEC tray

RELIABILITY

Moisture Sensitivity Level

JEDEC Level 2A, 260°C Reflow

Temperature Cycling

Condition C (–65°C to 150°C),

1000 cycles

High Temp Storage

150°C, 1000 hrs

Pressure Cooker Test

121°C/100%RH/2atm, 168 hrs

Temperature/Humidity Test

85°C/85% RH, 1000 hrs

Unbiased HAST

130°C/85% RH/2 atm, 96 hrs

CROSS-SECTION

FLGA-SD

PACKAGE CONFIGURATIONS

Body Sizes (mm)

4x4 to 13x13

Terminal Count

8 to 200

Terminal Pitch (mm)

0.5 to 0.8

Typ. Pkg. Thickness

TFLGA-SD: 1.2mm

VFLGA-SD: 1.0mm max.

WFLGA-SD: 0.8mm max.

ELECTRICAL PERFORMANCE

Electrical parasitic data is highly dependent on the package layout. 3D electrical simulation can be used on the specific package design

to provide the best prediction of electrical behavior. First order approximations can be calculated using parasitics per unit length for the

constituents of the signal path. Data below is for a frequency of 100MHz and assumes 1.0 mil gold bonding wire.

Conductor

Length

Resistance

Inductance

Inductance

Capacitance

Capacitance

Component

(mm)

(mOhms)

(nH)

Mutual (nH)

(pF)

Mutual (pF)

Wire

2

120

1.65

0.45 - 0.85

0.10

0.01 - 0.02

Net (2L)

2 - 7

25 -110

1.10 - 4.35

0.25 - 2.27

0.20 - 0.90

0.05 - 0.41

Total (2L)

4 - 0

145 - 230

2.75 - 6.00

0.70 - 3.12

0.30 - 1.00

0.06 - 0.43

Wire

2

120

1.65

0.45 - 0.85

0.10

0.01 - 0.02

Net (4L)

2 - 7

25 - 110

0.70 - 2.95

0.17 - 1.57

0.30 - 1.05

0.05 - 0.41

Total (4L)

4 - 9

145 - 230

2.35 - 4.60

0.62 - 2.42

0.40 - 1.15

0.06 - 0.43

Note: Net = Total Trace Length + Via