STA335BWSQS datasheet(60/70 Pages) STMICROELECTRONICS

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STA335BWSQS

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6.15

Fault detect recovery constant registers (addr 0x2B to 0x2C)

FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is asserted, the

TRISTATE output is immediately asserted low and held low for the time period specified by

this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The

default value of 0x000C specifies approximately 0.1 ms.

6.16

Device status register (addr 0x2D)

This read-only register provides fault and thermal-warning status information from the power

control block. Logic value 1 for faults or warning means normal state. Logic 0 means a fault

or warning detected on power bridge. The PLLUL = 1 means that the PLL is not locked.

PLLUL: 0 = PLL locked, 1 = PLL not locked.

FAULT: 0 = fault detected on power bridge, 1 = normal operation

UVFAULT: 0 = VCCx internally detected < undervoltage threshold.

OVFAULT: 0 = VCCx internally detected > overvoltage threshold.

OCFAULT: 0 = overcurrent fault detected

OCWARN: 0 = overcurrent warning.

TFAULT: 0 = thermal fault. Junction temperature over limit detection.

TWARN: 0 = thermal warning. The junction temperature is close to the fault condition.

FDRC15

FDRC14

FDRC13

FDRC12

FDRC11

FDRC10

FDRC9

FDRC8

000

FDRC7

FDRC6

FDRC5

FDRC4

FDRC3

FDRC2

FDRC1

FDRC0

110

PLLUL

FAULT

UVFAULT

OVFAULT

OCFAULT

OCWARN

TFAULT

TWARN

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