Control/Status Register (0Fh)

Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit

indicates that the oscillator either is stopped or was

stopped for some period and may be used to judge the

validity of the timekeeping data. This bit is set to logic 1

any time that the oscillator stops. The following are

examples of conditions that can cause the OSF bit to

be set:

1) The first time power is applied.

insufficient to support oscillation.

3) The

EOSC bit is turned off in battery-backed mode.

4) External influences on the crystal (i.e., noise, leak-

age, etc.).

This bit remains at logic 1 until written to logic 0.

Bit 6: Battery-Backed 32kHz Output (BB32kHz). This

(provided EN32kHz is enabled). If BB32kHz = 0, the

Bits 5 and 4: Conversion Rate (CRATE1 and

CRATE0). These two bits control the sample rate of the

TCXO. The sample rate determines how often the tem-

perature sensor makes a conversion and applies com-

pensation to the oscillator. Decreasing the sample rate

decreases the overall power consumption by decreas-

ing the frequency at which the temperature sensor

operates. However, significant temperature changes

that occur between samples may not be completely

compensated for, which reduce overall accuracy.

When a new conversion rate is written to the register, it

may take up to the new conversion rate time before the

conversions occur at the new rate.

Bit 3: Enable 32kHz Output (EN32kHz). This bit indi-

cates the status of the 32kHz pin. When set to logic 1,

the 32kHz pin is enabled and outputs a 32.768kHz

square-wave signal. When set to logic 0, the 32kHz pin

goes low. The initial power-up state of this bit is logic 1,

and a 32.768kHz square-wave signal appears at the

32kHz pin after a power source is applied to the DS3232

(if the oscillator is running).

Bit 2: Busy (BSY). This bit indicates the device is busy

executing TCXO functions. It goes to logic 1 when the

conversion signal to the temperature sensor is asserted

and then is cleared when the conversion is complete.

Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag

bit indicates that the time matched the alarm 2 regis-

ters. If the A2IE bit is logic 1 and the INTCN bit is set to

logic 1, the

INT/SQW pin is also asserted. A2F is

cleared when written to logic 0. This bit can only be

written to logic 0. Attempting to write to logic 1 leaves

the value unchanged.

Bit 0: Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag

bit indicates that the time matched the alarm 1 regis-

ters. If the A1IE bit is logic 1 and the INTCN bit is set to

logic 1, the

INT/SQW pin is also asserted. A1F is

cleared when written to logic 0. This bit can only be

written to logic 0. Attempting to write to logic 1 leaves

the value unchanged.

Integrated Crystal and SRAM

14

____________________________________________________________________

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

NAME:

OSF

BB32kHz

CRATE1

CRATE0

EN32kHz

BSY

A2F

A1F

POR*:

110

01

000

Control/Status Register (0Fh)

CRATE1

CRATE0

SAMPLE RATE

(seconds)

00

64

01

128

10

256

11

512