DS3232S datasheet(6/18 Pages) MAXIM

6 / 18 page

Extremely Accurate I2C RTC with

Integrated Crystal and SRAM

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Data Transfer on I2C Serial Bus

SDA

SCL

tHD:STA

tLOW

tHIGH

tBUF

tHD:DAT

tSU:DAT

REPEATED

START

tSU:STA

tHD:STA

tSU:STO

tSP

STOP

START

Note 1: Limits at -40°C are guaranteed by design and not production tested.

Note 2: All voltages are referenced to ground.

Note 3: ICCA—SCL clocking at max frequency = 400kHz.

Note 4: Current is the averaged input current, which includes the temperature conversion current.

Note 5: The RST pin has an internal 50kΩ (nominal) pullup resistor to VCC.

Note 6: After this period, the first clock pulse is generated.

Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal)

to bridge the undefined region of the falling edge of SCL.

Note 8: The maximum tHD:DAT needs only to be met if the device does not stretch the low period (tLOW) of the SCL signal.

Note 9: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ 250ns must then be met. This

is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the

low period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns

before the SCL line is released.

Note 10: CB—total capacitance of one bus line in pF.

Note 11: Minimum operating frequency of the I2C interface is imposed by the timeout period.

Note 12: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of

0V ≤ VCC ≤ VCC(MAX) and 2.3V ≤ VBAT ≤ 3.4V.

Note 13: This delay only applies if the oscillator is enabled and running. If the EOSC bit is 1, tREC is bypassed and RST immediately

goes high.

WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may

cause loss of data.

DS3232S Datasheet(PDF) 6 Page - Maxim Integrated Products