As noted in Section 6.2 Output capacitor selection, two different kinds of network can compensate the loop,

depending on the value of fzESR, lower or higher than the regulator required bandwidth.

In the following two paragraphs the guidelines to select the type II and type III compensation network are

illustrated.

6.4.1

Type II compensation network

If the equivalent series resistance (RES) of the output capacitor introduces a zero with a frequency lower than the

desired bandwidth (that is: 2π

∗RES∗CO>1/BW), this zero helps stabilize the loop. Electrolytic capacitors show

non-negligible ESR (>30 mΩ typically), so with this kind of output capacitor the type II network combined with the

zero of the ESR allows the loop to be stabilized.

Figure 11. Type II compensation network

The type II compensation network transfer function, from VOUT to COMP, is computed in the equation below:

GCOMPII(s)=−ZF(s)RU=− 1RU⋅ 1+sCFRF

s⋅(CF+CP)⋅(1+sCF//CPRF

=−1⋅ 1+ s2π⋅fZ1

s2π⋅fP0⋅1+ s2π⋅fP1

(20)

fZ1= 12π⋅CFRF;fP0= 1

2π⋅(CF+CP)⋅RU;fP1= 1

2π⋅CF//CPRF

(21)

The following suggestions can be followed for a quite common compensation strategy, assuming that CP<<CF.

•

Starting from Eq. (19) in case of a type II compensation network and electrolytic output capacitors, the

control loop gain module at s=2π*FBW allows RF/RU ratio to be fixed:

GLOOP,II(s=2π⋅fBW) ≅ 1kFF⋅ fLC2fzESR⋅RFRU⋅ 1fBW=1

(22)

After choosing the regulator bandwidth (typically FBW<0.2*FSW ) and a value for RU, usually between 1 kΩ and 50

kΩ, in order to achieve CF and CP not comparable with a parasitic capacitance of the board, the RF required value

is computed by Eq. (22).

•

Select CF in order to place FZ1 below FLC (typically 0.1*FLC)

•

Select CP in order to place FP1 at 0.5*FSW

CF= 1

2π⋅RF⋅0.1⋅fLC;CP= 1

2π⋅RF⋅0.5⋅fSW

(23)

The resultant control loop and other transfer functions gain are shown in Figure 12. Type II compensation - Bode

plot

A7987

Compensation network

DS12928 - Rev 3

page 18/36