Figure 27. Negative buck-boost schematic example

+

+ C6

47uF

EN

R8

47k

R9

N.M.

C10

100nF

R3

100k

VIN

C7

100nF

GND

C11

220pF

R6 2.7k

C9

100nF

GND

R4

4.7

R1

47k

C8

4.7nF

R5

560

-VOUT

D1

U1

A7987

PGOOD

12

VIN

3

SS

6

SYNCH

7

FSW

10

ILIM

11

COMP

8

EN

5

FB

9

GND

16

VCC

4

LX

13

LX

14

VIN

2

VBIAS

1

BOOT

15

TP

17

R2

1.6k

GND PLANE

IC GND

L1

47uH

Figure 28. Negative buck-boost PCB layout (top)

Figure 29. Negative buck-boost PCB layout (bottom)

Eq. (33) and Eq. (34) for positive buck-boost can be used to program the output voltage and estimate the working

duty cycle, assuming for VOUT a positive voltage. The other considerations summarized in the previous section

are also applied to the inverting buck-boost.

In this topology the device GND is shorted to VOUT, so the resulting voltage stress on the integrated power MOS

is the sum of VIN and VOUT. Consequently, the maximum input voltage must be lower than:

VIN≤VIN,MAX−VOUT

(39)

VIN,MAX = 61 V is the maximum operating input voltage for the A7987, as shown in Table 5. Electrical

characteristics.

Therefore, if the output voltage is -24 V, the maximum operating input voltage is close to 36 V, if also the

freewheeling diode has the same reverse voltage ratings.

For control loop stability analysis and compensation, the transfer function model and considerations summarized

in the previous section are also applied to this topology.

A7987

Negative buck-boost

DS12928 - Rev 3

page 28/36