ADF7025 datasheet(16/44 Pages) AD

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ADF7025

Rev. A | Page 16 of 44

Analog Lock Detect

This N-channel open-drain lock detect should be operated with

an external pull-up resistor of 10 kΩ nominal. When a lock has

been detected, this output is high with narrow low-going pulses.

Voltage Regulators

The ADF7025 contains four regulators to supply stable voltages

to the part. The nominal regulator voltage is 2.3 V. Each regulator

should have a 100 nF capacitor connected between VREG and

GND. When CE is high, the regulators and other associated

circuitry are powered on, drawing a total supply current of 2 mA.

Bringing the chip-enable pin low disables the regulators,

reduces the supply current to less than 1 µA, and erases all

values held in the registers. The serial interface operates from

a regulator supply; therefore, to write to the part, the user must

have CE high and the regulator voltage must be stabilized.

Regulator status (VREG4) can be monitored using the regulator

ready signal from MUXOUT.

Loop Filter

The loop filter integrates the current pulses from the charge

pump to form a voltage that tunes the output of the VCO to the

desired frequency. It also attenuates spurious levels generated by

the PLL. A typical loop filter design is shown in Figure 22.

CHARGE

PUMP OUT

VCO

Figure 22. Typical Loop Filter Configuration

In general, a loop filter bandwidth (LBW) of between the data

rate and twice the data rate is recommended. Widening the

LBW excessively reduces the time spent jumping between

frequencies, but it can cause insufficient spurious attenuation.

Narrow-loop bandwidths can result in the loop taking long

periods of time to attain lock. For the ADF7025 in receive mode,

the loop filter bandwidth affects the close-in blocking perform-

ance. The narrower the bandwidth of the loop filter, the greater

the close-in interference resilience of the receiver.

Careful design of the loop filter is critical to obtaining accurate

FSK modulation. The free design tool ADIsimPLL can be used

to design loop filters for the ADF7025.

N Counter

The feedback divider in the ADF7025 PLL consists of an 8-bit

integer counter and a 14-bit Σ-∆ Fractional-N divider. The

integer counter is the standard pulse-swallow type common in

PLLs. This sets the minimum integer divide value to 31.

The fractional divide value gives very fine resolution at the

output, where the output frequency of the PLL is calculated as

)

(

Fractional

Integer

XTAL

OUT

VCO

THIRD-ORDER

Σ-∆ MODULATOR

PFD/

CHARGE

PUMP

INTEGER-N

FRACTIONAL-N

REFERENCE IN

Figure 23. Fractional-N PLL

The combination of the Integer-N (maximum = 255) and the

Fractional-N (maximum = 16383/16384) gives a maximum N

divider of 255 + 1. Therefore, the minimum usable PFD is

PDFMIN [Hz] = Maximum Required Output Frequency/(255 + 1)

For example, when operating in the European 868 MHz to

870 MHz band, PFDMIN equals 3.4 MHz.

Voltage Controlled Oscillator

To minimize spurious emissions, the on-chip VCO operates

from 1732 MHz to 1856 MHz. The VCO signal is then divided

by 2 to give the required frequency for the transmitter and the

required LO frequency for the receiver.

The VCO should be re-centered, depending on the required

frequency of operation, by programming the VCO adjust bits

R1_DB [20:21].

For operation in the 862 MHz to 870 MHz band, it is recom-

mended to use a VCO bias of at least Setting 10 and to set the

VCO adjust bit to Setting 0. For operation in the 902 MHz to

928 MHz band, it is recommended to use a VCO bias of at least

Setting 12 and to set the VCO adjust bit to Setting 3. This is to

ensure correct operation under all conditions.

The VCO is enabled as part of the PLL by the PLL-enable bit,

R0_DB28.

An additional frequency divide-by-2 is included to allow

operation in the lower 431 MHz to 464 MHz bands. To enable

operation in these bands, R1_DB13 should be set to 1. The

VCO needs an external 22 nF between the VCO and the

regulator to reduce internal noise.

ADF7025 Datasheet(PDF) 16 Page - Analog Devices

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