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LMK0483PAP/EM Datasheet(PDF) 37 Page - Texas Instruments |
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LMK0483PAP/EM Datasheet(HTML) 37 Page - Texas Instruments |
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37 / 102 page  8.4.3 Distribution Mode Figure 8-15 shows the use case of distribution mode. As in all the other use cases, OSCIN to OSCOUT can be used as a buffer to OSCIN or from clock distribution path through CLKOUT6, CLKOUT8, or the SYSREF divider. At high frequency, the input impedance to FIN0/FIN1 is low and a resistive pad is recommended for matching. SYSREF Digital Delay Analog Delay OSCIN_P 7 Blocks Up to 14 Clock or SYSREF Outputs OSCOUT_P OSCOUT_N SYSREF Digital Delay Analog Delay SYSREF Digital Delay Analog Delay 7 Blocks OSCIN_N CLKIN1_P/FIN1_P CLKIN1_N/FIN1_N CLKOUT6/8 Device Clock Divider Digital Delay Analog Delay FIN0_P FIN0_N ÷2 CLKIN1_P/FIN1_P CLKIN1_N/FIN1_N Global SYSREF Divider and Delay CLKOUTx_P CLKOUTx_N CLKOUTx_P CLKOUTx_N Figure 8-15. Simplified Functional Block Diagram for Distribution Mode 8.5 Programming The device is programmed using 24-bit registers. Each register consists of a 1-bit command field (R/W), a 15-bit address field (A14 to A0) and a 8-bit data field (D7 to D0). The contents of each register is clocked in MSB first (R/W), and the LSB (D0) last. During programming, the CS* signal is held low. The serial data is clocked in on the rising edge of the SCK signal. After the LSB is clocked in, the CS* signal goes high to latch the contents into the shift register. TI recommends to program registers in numeric order (for example, 0x000 to 0x555 with exceptions noted in the Recommended Programming Sequence). Each register consists of one or more fields which control the device functionality. See the Electrical Characteristics table and Figure 6-1 for timing details. 8.5.1 Recommended Programming Sequence Registers are generally programmed in numeric order with 0x000 being the first and 0x555 being the last register programmed. The recommended programming sequence from POR involves: 1. Program register 0x000 with RESET = 1. 2. Program defined registers from 0x000 to 0x165. 3. If PLL2 is used, program 0x173 with PLL2_PD and PLL2_PRE_PD clear to allow PLL2 to lock after PLL2_N is programmed. 4. Continue programming defined registers from 0x166 to 0x555. Note When using the internal VCO, PLL2_N registers 0x166, 0x167, and 0x168 must be programmed after other PLL2 dividers are programed to ensure proper VCO frequency calibration. This is also true for PLL2_N_CAL registers 0x163, 0x164, 0x165 when PLL2_NCLK_MUX = 1. So if any divider such as PLL2_R is altered to change the VCO frequency, the VCO calibration must be run again by programming PLL2_N. Power up PLL2 by setting PLL2_PRE_PD = 0 and PLL2_PD = 0 in register 0x173 before programming PLL2_N. www.ti.com LMK04832-SEP SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: LMK04832-SEP |
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