LMK0483PAPSLASHEM datasheet(16/102 Pages) TI

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8 Detailed Description

8.1 Overview

This device is very flexible to meet many application requirements. Use cases include dual loop, dual loop

0-delay nested, dual loop 0-delay cascaded, single loop, single loop 0-delay, and clock distribution.

The device may be used in JESD204B/C systems by providing a device clock and SYSREF to target devices,

however traditional (non-JESD204B/C) systems are possible by programming pairs of outputs to share the clock

divider or any mix of JESD204B/C and traditional outputs.

8.1.1 Differences from the LMK04832

The LMK04832 is a widely known device that is similar to this device. However, these devices are not the same

and there are some differences.

Table 8-1. Differences Between the LMK04832-SEP and LMK04832

Attribute

LMK04832

LMK04832-SEP

Radiation Hardened

50 MeV

Temperature

–40ºC to +85ºC

–55ºC to +125ºC

Package

10 × 10 mm

Pin Rotation

n/a

Rotated 180° from LMK04832

6.4 GHz CLK/VCO Input Pin

No, Pins 8/9 are NC

Yes, Pins 40/41 are FIN0_P/FIN0_N

Pin After SYNC/SYSREFREQ Pin

NC (Pin 7)

GND (Pin 39)

Programming Speed

5 MHz

2.5 MHz

8.1.1.1 Jitter Cleaning

The dual loop PLL architecture provides the lowest jitter performance over a wide range of output frequencies

and phase noise integration bandwidths. The first stage PLL (PLL1) is driven by an external reference clock and

uses an external VCXO to provide a frequency accurate, low phase noise reference clock for the second stage

frequency multiplication PLL (PLL2).

PLL1 typically uses a narrow loop bandwidth (typically 10 Hz to 200 Hz) to retain the frequency accuracy of the

reference clock input signal while at the same time suppressing the higher offset frequency phase noise that

the reference clock may have accumulated along its path or from other circuits. This cleaned reference clock

provides the reference input to PLL2.

The low phase noise reference provided to PLL2 allows PLL2 to operate with a wide loop bandwidth (typically 50

kHz to 200 kHz). The loop bandwidth for PLL2 is chosen to take advantage of the superior high offset frequency

phase noise profile of the internal VCO and the good low offset frequency phase noise of the reference VCXO.

Ultra-low jitter is achieved by allowing the phase noise of the external VCXO to dominate the final output phase

noise at low offset frequencies and the phase noise of the internal VCO to dominate the final output phase noise

at high offset frequencies. This results in best overall phase noise and jitter performance.

8.1.1.2 JEDEC JESD204B/C Support

This device clocks up to seven JESD204B/C targets using seven device clocks and seven SYSREF clocks and

allows every clock output to be configured as a device clock or SYSREF clock.

LMK04832-SEP

SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022

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LMK0483PAP/EM Datasheet(PDF) 16 Page - Texas Instruments

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